The integration of Si-based resonant interband

eports the first demonstration of the integration of CMOS and Si/SiGe resonant interband tunnel diode (RITD). In Si-based material, recent breakthrough in Si/SiGe RITD grown using molecular beam epitaxy (MBE) made the integration with CMOS possible. The resultant devices enabled the realization of RITD CMOS circuitry, and a NMOS-RITD MOBILE latch was demonstrated in Si, all enabling digital and ternary circuit design for density storag

Quantum and spin-based tunneling devices for memory systems

Rapid developments in information technology, such as internet, portable computing, and wireless communication, create a huge demand for fast and reliable ways to store and process information. Thus far, this need has been paralleled with the revolution in solid-state memory technologies. Memory devices, such as SRAM, DRAM, and flash, have been widely used in most electronic products. The primary strategy to keep up the trend is miniaturization. CMOS devices have been scaled down beyond sub-45 nm, the size of only a few atomic layers. Scaling, however, will soon reach the physical limitation of the material and cease to yield the desired enhancement in device performance. In this thesis, an alternative method to scaling is proposed and successfully realized. The proposed scheme integrates quantum devices, Si/SiGe resonant interband tunnel diodes (RITD), with classical CMOS devices forming a microsystem of disparate devices to achieve higher performance as well as higher density. The device/circuit designs, layouts and masks involving 12 levels were fabricated utilizing a process that incorporates nearly a hundred processing steps. Utilizing unique characteristics of each component, a low-power tunneling-based static random access memory (TSRAM) has been demonstrated. The TSRAM cells exhibit bistability operation with a power supply voltage as low as 0.37 V. Various TSRAM cells were also constructed and their latching mechanisms have been extensively investigated. In addition, the operation margins of TSRAM cells are evaluated based on different device structures and temperature variation from room temperature up to 200oC. The versatility of TSRAM is extended beyond the binary system. Using multi-peak Si/SiGe RITD, various multi-valued TSRAM (MV-TSRAM) configurations that can store more than two logic levels per cell are demonstrated. By this virtue, memory density can be substantially increased. Using two novel methods via ambipolar operation and utilization of enable/disable transistors, a six-valued MV-TSRAM cell are demonstrated. A revolutionary novel concept of integrating of Si/SiGe RITD with spin tunnel devices, magnetic tunnel junctions (MTJ), has been developed. This hybrid approach adds non-volatility and multi-valued memory potential as demonstrated by theoretical predictions and simulations. The challenges of physically fabricating these devices have been identified. These include process compatibility and device design. A test bed approach of fabricating RITD-MTJ structures has been developed. In conclusion, this body of work has created a sound foundation for new research frontiers in four different major areas: integrated TSRAM system, MV-TSRAM system, MTJ/RITD-based nonvolatile MRAM, and RITD/CMOS logic circuits

Full-Wafer DMOS Fabrication at RIT

A well understanding of basic structure of Double Diffused Metal Oxide Semiconductor (DMOS) and the concept of segmented large capacitor creates possibility to produce a full-wafer DMOS. Using the Mylar Mask Technology, the final metal layer can be patterned accordingly so that to leave out any damaged fragments. Thus, it will increase the possibility of higher yield. Most of the basic fabrication processes will be done at RIT microelectronics lab facilities, and the functionality tests will be conducted at Naval Research Lab. Therefore, this paper is intended to give a general overview of concepts involved and the fabrication processes

QUANTUM AND SPIN TUNNEL DEVICES FOR MEMORY APPLICATIONS

The increasing trend towards portable digital electronics and wireless communication devices has driven the advancement of several memory technologies in the last couple of decades. The standards of performance are becoming more stringent, posing several challenges from device design, circuit architecture, and manufacturing capability. The current commercially available memory devices, such as SRAM, DRAM, and Flash, offer enhanced performance in one aspect while sacrificing on other areas. Memory technologies that utilize quantum tunneling based devices, such as tunneling diodes have been sought as a viable solution. The tunneling property allows for fast switching. The low operating voltage results in low standby power. Recent breakthroughs by the authors in monolithic integration of SiGe resonant interband tunnel diodes (RITDs) with CMOS devices offer novel architectures for memory applications. The latest developments demonstrated a refresh-free Si-based tunneling static random access memory (TSRAM), exhibiting an enhanced signal to noise ratio. In addition, its basic cell can be expanded into a multi-level memory by utilizing several tunnel diodes connected in series. This would substantially increase memor

Diffusion barrier cladding in Si/SiGe resonant interband tunneling diodes and their patterned growth on PMOS source/drain regions

Abstract—Si/SiGe resonant interband tunnel diodes (RITDs) employing-doping spikes that demonstrate negative differential resistance (NDR) at room temperature are presented. Efforts have focused on improving the tunnel diode peak-to-valley current ratio (PVCR) figure-of-merit, as well as addressing issues of manufacturability and CMOS integration. Thin SiGe layers sandwiching the B-doping spike used to suppress B out-diffusion are discussed. A room-temperature PVCR of 3.6 was measured with a peak current density of 0.3 kA/cmP. Results clearly show that by introducing SiGe layers to clad the B-doping layer, B diffusion is suppressed during post-growth annealing, which raises the thermal budget. A higher RTA temperature appears to be more effective in reducing defects and results in a lower valley current and higher PVCR. RITDs grown by selective area molecular beam epitaxy (MBE) have been realized inside of low-temperature oxide openings, with performance comparable with RITDs grown on bulk substrates. Index Terms—CMOS compatibilty, dopant diffusion, Ge-Si alloys, low-temperature oxide, molecular beam epitaxy, negative differential resistance, patterned growth, rapid thermal annealing, resonant interband tunneling diodes, silicon. I