Salicide-Like Process for the Formation of Gate and Source Contacts in 4H-SiC TSI-VJFETs

International audienceThe self-aligned approach allowed to fabricate 4H-SiC VJFETs with contact lithography with only 4 lithography steps. The main problem of this approch was the gate-source leakage current. In order to address this issue, a salicide process has been adopted resulting in a substantial reduction of the gate-source leakage current. The success of this approch paved the way for fabricating high power 4H-SiC devices with extremely low fabrication cost

A Continuous Semi-Empirical VJFET Capacitance Model from Sub to above Threshold Regime

International audienceThis paper presents and discusses the depletion mechanisms that dominate in a TSI-VJFET under different bias conditions as expressed by the gate-source (CGS) and gate-drain (CGD) capacitances. It is shown that at pinch off the dominant capacitance is the drift capacitance and that in conduction the drain source voltage plays a significant role in channel’s formation. Furthermore a semi empirical capacitance model is introduced. CGS and CGD are modeled below and above threshold voltage by considering parallel plate capacitors with different plate configuration in te two cases. Then, the derived expressions are unified using a transition function that preserves the continuity of the model. The model was adjusted and fitted adequately to measured CV data from fabricated TSI-VJFET

On the Optimum Determination and Use of SiC VJFET Threshold Voltage

International audienceThe threshold voltage of SiC JFETs has been determined from transfer characteristics by employing methods commonly used in the case of MOSFETs. The extracted values have been compared with the value determined from the fitting of experimental transfer characteristics with the Schockley model equation. Moreover, the variation of the extracted threshold voltage values with respect to channel width has been employed to determine the channel concentration without taking into account the Vbi value

4H-SiC VJFETs with Self-Aligned Contacts

International audienceTrenched-implanted-gate 4H–SiC vertical-channel JFET (TI-VJFET) have been fabricated with self-aligned nickel silicide source and gate contacts using a process sequence that greatly reduces process complexity as it includes only four lithography steps. The effect of the channel geometry on the electrical characteristics has been studied by varying its length (0.3 and 1.2μm) and its width (1.5-5μm). The transistors exhibited high current handling capabilities (Direct Current density 330A/cm2). The output current reduces with the increase of the measurements temperature due to the decrease of the electron mobility value. The voltage breakdown exhibits a triode shape, which is typical for a static-induction transistor operation

Modelling of 4H-SiC VJFETS with self-aligned contacts

Summarization: Purely vertical 4H-SiC JFETs have been modeled by using three different approaches: the analytical model, the finite element model and the compact model. The results of the modelling have been compared with experimental results obtained on a series of fabricated self-aligned devices with two different channel lengths (0.3 and 1.1μm) and various channel widths (1.5, 2, 2.5, 3, 4 and 5 μm). For all the considered models I-V and C-V characteristics could be satisfactorily simulated.Παρουσιάστηκε στο: 16th International Conference on Silicon Carbide and Related Material