Surface energy engineering of graphene

Contact angle goniometry is conducted for epitaxial graphene on SiC. Although only a single layer of epitaxial graphene exists on SiC, the contact angle drastically changes from 69{\deg} on SiC substrates to 92{\deg} with graphene. It is found that there is no thickness dependence of the contact angle from the measurements of single, bi, and multi layer graphene and highly ordered pyrolytic graphite (HOPG). After graphene is treated with oxygen plasma, the level of damage is investigated by Raman spectroscopy and correlation between the level of disorder and wettability is reported. By using low power oxygen plasma treatment, the wettability of graphene is improved without additional damage, which can solve the adhesion issues involved in the fabrication of graphene devices

Inkjet printed circuits with two-dimensional semiconductor inks for high-performance electronics

Air-stable semiconducting inks suitable for complementary logic are key to create low-power printed integrated circuits (ICs). High-performance printable electronic inks with two-dimensional materials have the potential to enable the next generation of high performance, low-cost printed digital electronics. Here we demonstrate air-stable, low voltage (< 5 V) operation of inkjet-printed n-type molybdenum disulfide (MoS2) and p-type indacenodithiophene-co-benzothiadiazole (IDT-BT) field-effect transistors (FETs), estimating a switching time of {\tau} ~ 3.3 {\mu}s for the MoS2 FETs. We achieve this by engineering high-quality MoS2 and air-stable IDT-BT inks suitable for inkjet-printing complementary pairs of n-type MoS2 and p-type IDT-BT FETs. We then integrate MoS2 and IDT-BT FETs to realise inkjet-printed complementary logic inverters with a voltage gain |Av| ~ 4 when in resistive load configuration and |Av| ~ 1.36 in complementary configuration. These results represent a key enabling step towards ubiquitous long-term stable, low-cost printed digital ICs

Hydrostatic strain enhancement in laterally confined SiGe nanostripes

Strain-engineering in SiGe nanostructures is fundamental for the design of optoelectronic devices at the nanoscale. Here we explore a new strategy, where SiGe structures are laterally confined by the Si substrate, to obtain high tensile strain avoiding the use of external stressors, and thus improving the scalability. Spectro-microscopy techniques, finite element method simulations and ab initio calculations are used to investigate the strain state of laterally confined Ge-rich SiGe nano-stripes. Strain information is obtained by tip enhanced Raman spectroscopy with an unprecedented lateral resolution of ~ 30 nm. The nano-stripes exhibit a large tensile hydrostatic strain component, which is maximum at the center of the top free surface, and becomes very small at the edges. The maximum lattice deformation is larger than the typical values of thermally relaxed Ge/Si(001) layers. This strain enhancement originates from a frustrated relaxation in the out-of-plane direction, resulting from the combination of the lateral confinement induced by the substrate side walls and the plastic relaxation of the misfit strain in the (001) plane at the SiGe/Si interface. The effect of this tensile lattice deformation at the stripe surface is probed by work function mapping, performed with a spatial resolution better than 100 nm using X-ray photoelectron emission microscopy. The nano-stripes exhibit a positive work function shift with respect to a bulk SiGe alloy, quantitatively confirmed by electronic structure calculations of tensile strained configurations. The present results have a potential impact on the design of optoelectronic devices at a nanometer length scale.Comment: 40 pages, 11 figures, submitted to Physical Review

Size Evolution of Ordered SiGe Islands Grown by Surface Thermal Diffusion on Pit-Patterned Si(100) Surface

The ordered growth of self-assembled SiGe islands by surface thermal diffusion in ultra high vacuum from a lithographically etched Ge stripe on pit-patterned Si(100) surface has been experimentally investigated. The total surface coverage of Ge strongly depends on the distance from the source stripe, as quantitatively verified by Scanning Auger Microscopy. The size distribution of the islands as a function of the Ge coverage has been studied by coupling atomic force microscopy scans with Auger spectro-microscopy data. Our observations are consistent with a physical scenario where island positioning is essentially driven by energetic factors, which predominate with respect to the local kinetics of diffusion, and the growth evolution mainly depends on the local density of Ge atoms

Ordered Arrays of SiGe Islands from Low-Energy PECVD

SiGe islands have been proposed for applications in the fields of microelectronics, optoelectronics and thermoelectrics. Although most of the works in literature are based on MBE, one of the possible advantages of low-energy plasma-enhanced chemical vapor deposition (LEPECVD) is a wider range of deposition rates, which in turn results in the possibility of growing islands with a high Ge concentration. We will show that LEPECVD can be effectively used for the controlled growth of ordered arrays of SiGe islands. In order to control the nucleation of the islands, patterned Si (001) substrates were obtained by e-beam lithography (EBL) and dry etching. We realized periodic circular pits with diameters ranging from 80 to 300 nm and depths from 65 to 75 nm. Subsequently, thin films (0.8–3.2 nm) of pure Ge were deposited by LEPECVD, resulting in regular and uniform arrays of Ge-rich islands. LEPECVD allowed the use of a wide range of growth rates (0.01–0.1 nm s−1) and substrates temperatures (600–750°C), so that the Ge content of the islands could be varied. Island morphology was characterized by AFM, while μ-Raman was used to analyze the Ge content inside the islands and the composition differences between islands on patterned and unpatterned areas of the substrate

Inkjet Printed Circuits with 2D Semiconductor Inks for High-Performance Electronics

Funder: Imperial College London; Id: http://dx.doi.org/10.13039/501100000761Abstract: Air‐stable semiconducting inks suitable for complementary logic are key to create low‐power printed integrated circuits (ICs). High‐performance printable electronic inks with 2D materials have the potential to enable the next generation of high performance low‐cost printed digital electronics. Here, the authors demonstrate air‐stable, low voltage (<5 V) operation of inkjet‐printed n‐type molybdenum disulfide (MoS2), and p‐type indacenodithiophene‐co‐benzothiadiazole (IDT‐BT) field‐effect transistors (FETs), estimating an average switching time of τMoS2 ≈ 4.1 μs for the MoS2 FETs. They achieve this by engineering high‐quality MoS2 and air‐stable IDT‐BT inks suitable for inkjet‐printing complementary pairs of n‐type MoS2 and p‐type IDT‐BT FETs. They then integrate MoS2 and IDT‐BT FETs to realize inkjet‐printed complementary logic inverters with a voltage gain |Av| ≈ 4 when in resistive load configuration and |Av| ≈ 1.4 in complementary configuration. These results represent a key enabling step towards ubiquitous long‐term stable, low‐cost printed digital ICs

Enhanced Logic Performance with Semiconducting Bilayer Graphene Channels

Realization of logic circuits in graphene with an energy gap (EG) remains one of the main challenges for graphene electronics. We found that large transport EGs (>100 meV) can be fulfilled in dual-gated bilayer graphene underneath a simple alumina passivation top gate stack, which directly contacts the graphene channels without an inserted buffer layer. With the presence of EGs, the electrical properties of the graphene transistors are significantly enhanced, as manifested by enhanced on/off current ratio, subthreshold slope and current saturation. For the first time, complementary-like semiconducting logic graphene inverters are demonstrated that show a large improvement over their metallic counterparts. This result may open the way for logic applications of gap-engineered graphene.Comment: Accepted by ACS Nan

Science and technology roadmap for graphene, related two-dimensional crystals, and hybrid systems

We present the science and technology roadmap for graphene, related two-dimensional crystals, and hybrid systems, targeting an evolution in technology, that might lead to impacts and benefits reaching into most areas of society. This roadmap was developed within the framework of the European Graphene Flagship and outlines the main targets and research areas as best understood at the start of this ambitious project. We provide an overview of the key aspects of graphene and related materials (GRMs), ranging from fundamental research challenges to a variety of applications in a large number of sectors, highlighting the steps necessary to take GRMs from a state of raw potential to a point where they might revolutionize multiple industries. We also define an extensive list of acronyms in an effort to standardize the nomenclature in this emerging field.Peer ReviewedPostprint (published version

Gigahertz multi-transistor graphene integrated circuits

We review the potential of graphene in ultra-high speed circuits. To date, most of high-frequency graphene circuits typically consist of a single transistor integrated with a few passive components. The development of multi-transistor graphene integrated circuits operating at GHz frequencies can pave the way for applications in which high operating speed is traded off against power consumption and circuit complexity. Novel vertical and planar devices based on a combination of graphene and layered materials could broaden the scope and performances of future devices. © 2013 IEEE