Method And Apparatus For Improved Cumulative Yield Of On-Package Voltage Regulator Assembly

In high-power application-specific integrated circuits (ASICs), multiple voltage regulator ICs are required on the package to provide the required power to the ASIC. These underfill components on package are not reworkable and manufacturing flaws cannot be fixed, thus having a negative impact on the overall package yield. A system and method are proposed here to increase the package yield on ASICs by placing redundant voltage regulator ICs in addition to the multiple voltage regulator ICs operating in parallel on a semiconductor package. The redundancy ensures that the overall system in the package would be functional even with certain limited flawed ICs, which are then disabled. This method increases the cumulative assembly yield, with relatively small increase in cost and size. Furthermore, they allow a degree of freedom in the die size and power rating selection of voltage regulator ICs

In-Datacenter Performance Analysis of a Tensor Processing Unit

Many architects believe that major improvements in cost-energy-performance must now come from domain-specific hardware. This paper evaluates a custom ASIC---called a Tensor Processing Unit (TPU)---deployed in datacenters since 2015 that accelerates the inference phase of neural networks (NN). The heart of the TPU is a 65,536 8-bit MAC matrix multiply unit that offers a peak throughput of 92 TeraOps/second (TOPS) and a large (28 MiB) software-managed on-chip memory. The TPU's deterministic execution model is a better match to the 99th-percentile response-time requirement of our NN applications than are the time-varying optimizations of CPUs and GPUs (caches, out-of-order execution, multithreading, multiprocessing, prefetching, ...) that help average throughput more than guaranteed latency. The lack of such features helps explain why, despite having myriad MACs and a big memory, the TPU is relatively small and low power. We compare the TPU to a server-class Intel Haswell CPU and an Nvidia K80 GPU, which are contemporaries deployed in the same datacenters. Our workload, written in the high-level TensorFlow framework, uses production NN applications (MLPs, CNNs, and LSTMs) that represent 95% of our datacenters' NN inference demand. Despite low utilization for some applications, the TPU is on average about 15X - 30X faster than its contemporary GPU or CPU, with TOPS/Watt about 30X - 80X higher. Moreover, using the GPU's GDDR5 memory in the TPU would triple achieved TOPS and raise TOPS/Watt to nearly 70X the GPU and 200X the CPU.Comment: 17 pages, 11 figures, 8 tables. To appear at the 44th International Symposium on Computer Architecture (ISCA), Toronto, Canada, June 24-28, 201