A Scatter Search Approach for Multiobjective Selective Disassembly Sequence Problem

Disassembly sequence has received much attention in recent years. This work proposes a multiobjective optimization of model for selective disassembly sequences and maximizing disassembly profit and minimizing disassembly time. An improved scatter search (ISS) is adapted to solve proposed multiobjective optimization model, which embodies diversification generation of initial solutions, crossover combination operator, the local search strategy to improve the quality of new solutions, and reference set update method. To analyze the effect on the performance of ISS, simulation experiments are conducted on different products. The validity of ISS is verified by comparing the optimization effects of ISS and nondominated sorting genetic algorithm (NSGA-II)

A multimodal fusion method for Alzheimer’s disease based on DCT convolutional sparse representation

IntroductionThe medical information contained in magnetic resonance imaging (MRI) and positron emission tomography (PET) has driven the development of intelligent diagnosis of Alzheimer’s disease (AD) and multimodal medical imaging. To solve the problems of severe energy loss, low contrast of fused images and spatial inconsistency in the traditional multimodal medical image fusion methods based on sparse representation. A multimodal fusion algorithm for Alzheimer’ s disease based on the discrete cosine transform (DCT) convolutional sparse representation is proposed.MethodsThe algorithm first performs a multi-scale DCT decomposition of the source medical images and uses the sub-images of different scales as training images, respectively. Different sparse coefficients are obtained by optimally solving the sub-dictionaries at different scales using alternating directional multiplication method (ADMM). Secondly, the coefficients of high-frequency and low-frequency subimages are inverse DCTed using an improved L1 parametric rule combined with improved spatial frequency novel sum-modified SF (NMSF) to obtain the final fused images.Results and discussionThrough extensive experimental results, we show that our proposed method has good performance in contrast enhancement, texture and contour information retention

Improved Brain-Storm Optimizer for Disassembly Line Balancing Problems Considering Hazardous Components and Task Switching Time

Disassembling discarded electrical products plays a crucial role in product recycling, contributing to resource conservation and environmental protection. While disassembly lines are progressively transitioning to automation, manual or human–robot collaborative approaches still involve numerous workers dealing with hazardous disassembly tasks. In such scenarios, achieving a balance between low risk and high revenue becomes pivotal in decision making for disassembly line balancing, determining the optimal assignment of tasks to workstations. This paper tackles a new disassembly line balancing problem under the limitations of quantified penalties for hazardous component disassembly and the switching time between adjacent tasks. The objective function is to maximize the overall profit, which is equal to the disassembly revenue minus the total cost. A mixed-integer linear program is formulated to precisely describe and optimally solve the problem. Recognizing its NP-hard nature, a metaheuristic algorithm, inspired by human idea generation and population evolution processes, is devised to achieve near-optimal solutions. The exceptional performance of the proposed algorithm on practical test cases is demonstrated through a comprehensive comparison involving its solutions, exact solutions obtained using CPLEX to solve the proposed mixed-integer linear program, and those of competitive peer algorithms. It significantly outperforms its competitors and thus implies its great potential to be used in practice. As computing power increases, the effectiveness of the proposed methods is expected to increase further

A Low Mismatch Current Charge Pump Applied to Phase-Locked Loops

This paper presents a charge pump circuit with a wide output range and low current mismatch applied to phase-locked loops. In this designed structure, T-shaped analog switches are adopted to suppress the non-ideal effects of clock feedthrough, switching time mismatch, and charge injection. A source follower and current splitting circuits are proposed to improve the matching accuracy of the charging and discharging currents and reduce the current mismatch rate. A rail-to-rail high-gain amplifier with a negative feedback connection is introduced to suppress the charge-sharing effect of the charge pump. A cascode current mirror with a high output impedance is used to provide the charge and discharge currents for the charge pump, which not only improves the current accuracy of the charge pump but also increases the output voltage range. The proposed charge pump is designed and simulated based on a 65 nm CMOS process. The results show that when the power supply voltage is 1.2 V, the output current of the charge pump is 100 μA, the output voltage is in the range of 0.2~1 V, and the maximum current mismatch rate and current variation rate are only 0.21% and 1.4%, respectively

A Novel Radiation-Hardened CCDM-TSPC Compared with Seven Well-Known RHBD Flip-Flops in 180 nm CMOS Process

Numerous radiation-hardened-by-design (RHBD) flip-flops have been developed to increase the dependability of digital chips for space applications over the past two decades. In this paper, the radiation immunity and performance of seven well-known RHBD flip-flops are discussed. A novel cross-connected dual modular redundant true single-phase clock (TSPC) D flip-flop (CCDM-TSPC) is proposed. The presented CCDM-TSPC replaces the typical master-slave D flip-flop (MS-DFF) with the fundamental TSPC structure to shorten the circuit’s propagation time. All sensitive points in the circuit are radiation-hardened by using means of cross-connection. The simulation results of the SPECTRE tool show that CCDM-TSPC is completely immune to single-event upsets (SEUs). CCDM-TSPC reduces the C-Q delay by 75% and the layout area by 85% compared with the traditional triple modular redundancy D flip-flop (TMR-DFF)

Intelligent Spectrum Management and Trajectory Design for UAV-Assisted Cognitive Ambient Backscatter Networks

In this paper, we consider a novel Internet of Things (IoT) system in smart city called unmanned aerial vehicle- (UAV-) assisted cognitive backscatter network, where a UAV is employed as both a relay and a radio frequency source to help the data transmission between ground IoT backscatter devices (BDs) and a remote data center (DC). However, since the IoT applications are usually not assigned dedicated spectrum resource in smart cities, these data transmissions from BDs to the DC should share the licensed spectrum of cellular users (CUs). Therefore, we aim to maximize the minimum uplink throughput among all BDs while avoiding severe interference to CUs via joint spectrum management and UAV trajectory design. To solve the problem, we propose an iterative method utilizing block coordinated decent to partition the variables into two blocks. For the spectrum management problem, we first prove its convexity with the transmit power and time scheduling and then propose a two-step method to solve the two variables sequentially. For the UAV trajectory design problem, we resort to the fractional programming method to handle it. Simulation results demonstrate that the proposed algorithm can significantly increase the average max-min rate of the BDs while guaranteeing the acceptable interference to CUs with a fast convergence speed

A New Design Technique for a High-Speed and High dV/dt Immunity Floating-Voltage Level Shifter

This paper presents a high-speed level shifter with about 500 V/ns power supply slew immunity. In this designed structure, a narrow pulse-controlled current source is adapted to accelerate the voltage conversion and reduce the power consumption. A Fast-Slewing Circuit speeds up the operation of the level shifter based on the current comparison principle. Edge detection technology is used to filter the generated voltage noise and achieve high dV/dt immunity. The proposed level shifter simulated with the 0.18 μm BCD (bipolar-CMOS-DMOS) process shows fast responses with a typical delay of 1.49 ns and 500 V/ns dV/dt immunity in the 200 V high-voltage application, which only occupies a 0.022 mm2 active area with the 0.18 μm BCD process

Classification of Corn Stalk Lodging Resistance Using Equivalent Forces Combined with SVD Algorithm

Corn stalk lodging, which involves the breakage of the stalk below the ear following either bad weather, insect infestation or stormy rain, usually leads to harvest loss, increased harvesting time and higher drying costs. The objective of this study was to develop a method that can classify corn stalk lodging resistance. This method, which employed the maximum equivalent force exerted on a corn stalk, corresponding stalk agronomic traits, and the singular value decomposition (SVD) algorithm, showed that the five corn varieties with different stalk lodging resistance from two planting densities of 60,000 plants/ha and 75,000 plants/ha can be effectively classified. A customized device was designed to measure the equivalent forces. Three factors, including the planting density, the stalk diameter, and the maximum equivalent force with comprehensive contributions of −0.4603, 0.4196 and 0.4068, which are related to principal components, play an important role in the classification of corn stalk lodging resistance. The results showed that the corn stalk lodging resistance decreased with increase in planting density; however, with the increase in stalk diameter and maximum equivalent force, the lodging resistance significantly increased. Corn breeders can develop higher lodging resistance-based corn varieties by using this approach