Characterization of optical interconnects

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2000.Includes bibliographical references (p. 72-75).Interconnect has become a major issue in deep sub-micron technology. Even with copper and low-k dielectrics, parasitic effects of interconnects will eventually impede advances in integrated electronics. One technique that has the potential to provide a paradigm shift is optics. This project evaluates the feasibility of optical interconnects for distributing data and clock signals. In adopting this scheme, variation is introduced by the detector, the waveguides, and the optoelectronic circuit, which includes device, power supply and temperature variations. We attempt to characterize the effects of the aforementioned sources of variation by designing a baseline optoelectronic circuitry and fabricating a test chip which consists of the circuitry and detectors. Simulations are also performed to supplement the effort. The results are compared with the performance of traditional metal interconnects. The feasibility of optical interconnects is found to be sensitive to the optoelectronic circuitry used. Variation effects from the devices and operating conditions have profound impact on the performance of optical interconnects since they introduce substantial skew and delay in the otherwise ideal system.by Shiou Lin Sam.S.M

A control mechanism for sales associates in high-end retail

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.Includes bibliographical references (p. 121-123).The strength of the high-end retail industry has traditionally been in marketing and branding while management and operational efficiency lagged behind. In the face of changing client demographics and increased competition, improving operations through better data management and utilization could prove promising. In this work, we attempt to do so by focusing on a neglected area in high-end retail - management of the sales associates. Our first finding is the existence of a disconnect between the data collected and the data required for better control of the associates. Recognizing the gap, we sidestep it by tapping the knowledge of many experienced sales associates through field work. This knowledge is then funneled back to assist in modeling client behavior. The dynamics between an associate and his clients are modeled using an evolution model with stochastic client behavior. We show that under certain conditions, the optimal policy for an associate is a quasi-concave policy. In addition, we provide a methodology that would enable the associates to capture the full potential of a client while at the same time, allow management to reduce the variability in customer service within the store. The computational results indicate that such a mechanism, when compared to the commonly practiced policies, can achieve a substantial lift in revenue generated. In addition, the results also provide managerial insights and expose some common misconceptions.by Shiou Lin Sam.Ph.D

A Methodology for Modeling the Effects of Systematic Within-Die Interconnect and Device Variation on Circuit Performance

: We present a methodology to study the impact of spatial pattern dependent variation on circuit performance and implement the technique in a CAD framework. We investigate the effects of interconnect CMP and poly CD device variation on interconnect delay and clock skew in both aluminum and copper interconnect technology. Our results indicate that interconnect CMP variation strongly affects interconnect delay, while poly CD variation has a large impact on clock skew in a 1 GHz design. Given this circuit impact, CAD tools in the future must account for such systematic within-die variations. 1 Introduction Traditional statistical circuit analysis has focused mostly on random process and device variation [2,6]. However, recent studies have shown that systematic within-die (also referred to as intra-die or across chip) variation is a significant concern in high performance circuits [5,12]. For example, most of the variation resulting from chemical-mechanical polishing (CMP) of the inter-l..