Genetic variants in RET and risk of Hirschsprung's disease in Southeastern Chinese: a haplotype-based analysis

<p>Abstract</p> <p>Background</p> <p>Hirschsprung's disease (HSCR) is a classic oligogenic disorder. Except inactivating mutations of RET, some single nucleotide polymorphisms (SNPs) are identified to be associated with the risk of HSCR. This study was conducted to examine the impact of the haplotypes profile of the reported associated SNPs of RET on the risk of HSCR in a Southeastern Chinese population.</p> <p>Methods</p> <p>Genotypes of -5G > A (rs10900296), -1A > C (rs10900297), c135G > A (rs1800858), c1296A > G (rs1800860), and c2307T > G (rs1800861) were analyzed in 123 HSCR patients and 168 controls by polymerase chain reaction amplification and direct sequencing. Associations with risk of HSCR were estimated by odds ratio (OR) and their 95% confidence intervals (95% CI) using logistic regression.</p> <p>Results</p> <p>We observed a significantly increased risk of HSCR associated with the RET -5AA (OR = 17.75, 95% CI = 7.34-42.92), -1CC (OR = 10.89, 95% CI = 3.13-37.85), 135AA (OR = 13.61, 95% CI = 6.14-30.14), 1296GG (OR = 2.40, 95% CI = 1.38-4.18) or 2307GG (OR = 9.79, 95% CI = 4.28-22.43) respectively. The five SNPs were in strong linkage disequilibrium. The haplotype A-C-A-G-G (OR = 5.06, 95% CI = 1.97-12.99) and diplotype A-C-A-G-G/A-C-A-G-G (OR = 21.08, 95% CI = 5.28-84.09) was also associated with the increased risk of HSCR, indicating a cumulative effect of these SNPs on the susceptibility of HSCR.</p> <p>Conclusion</p> <p>These results support the hypothesis that common variations in RET pathway might play an important role in development of HSCR.</p

A Common SMAD7 Variant Is Associated with Risk of Colorectal Cancer: Evidence from a Case-Control Study and a Meta-Analysis

<div><h3>Background</h3><p>A common genetic variant, rs4939827, located in <em>SMAD7</em>, was identified by two recent genome-wide association (GWA) studies to be strongly associated with the risk of colorectal cancer (CRC). However, the following replication studies yielded conflicting results.</p> <h3>Method and Findings</h3><p>We conducted a case-control study of 641 cases and 1037 controls in a Chinese population and then performed a meta-analysis, integrating our and published data of 34313 cases and 33251 controls, to clarify the relationship between rs4939827 and CRC risk. In our case-control study, the dominant model was significant associated with increased CRC risk [Odds Ratio (OR) = 1.46; 95% confidence interval (95% CI), 1.19–1.80]. The following meta-analysis further confirmed this significant association for all genetic models but with significant between-study heterogeneity (all <em>P</em> for heterogeneity <0.1). By stratified analysis, we revealed that ethnicity, sample size, and tumor sites might constitute the source of heterogeneity. The cumulative analysis suggested that evident tendency to significant association was seen with adding study samples over time; whilst, sensitive analysis showed results before and after removal of each study were similar, indicating the highly stability of the current results.</p> <h3>Conclusion</h3><p>Results from our case-control study and the meta-analysis collectively confirmed the significant association of the variant rs4939827 with increased risk of colorectal cancer. Nevertheless, fine-mapping of the susceptibility loci defined by rs4939287 should be imposed to reveal causal variant.</p> </div

Lifetime reliability-aware digital synthesis

CMOS downscaling poses a growing concern for circuit lifetime reliability. Bias Temperature Instability (BTI) is a major source of transistor aging, causing a threshold voltage increase in CMOS devices and affecting circuit timing. This paper presents an aging mitigation approach that can be incorporated in standard synthesis. We propose a technique to restructure the logic expressions for aging-critical gates and to reduce the BTI stress duty cycle. A new technology mapping strategy is demonstrated, including a forward pass to select the proper cells and implement the optimized logic, and a backward pass to validate remapped circuits by restricting the negative slacks. The negative slacks produced in the mapping stage are eliminated by gate-level optimization, which aims to optimize a circuit to improve lifetime reliability under timing and area constraints. It employs a sensitivity metric that can be adjusted according to the design specifications to pick the most favorable transformation in terms of timing, lifetime or both. Our results show a 59.1% lifetime improvement with 0.86% area overhead on average. Compared with conventional over-design, a 28.29% higher lifetime improvement is realized. In addition, our approach can optimize a circuit under each corner case, considering both process variations and input data

Ageing-aware logic synthesis

CMOS wear-out mechanisms, especially bias temperature instability (BTI), cause growing concerns about circuit reliability. For a logic circuit, the BTI effect increases signal delays, eventually leading to timing violations. Due to the increased demand for circuit density, logic synthesis is currently a significant EDA process to design a circuit with many millions of transistors. Traditional synthesis process does not specifically consider the ageing effects. To ensure reliable operations during the expected lifetime of a circuit, it is necessary to incorporate BTI analysis and optimizations into logic synthesis. This chapter presents case studies about how state-of-the-art techniques can be used to enhance BTI lifetime reliability during synthesis and discusses the advantages and drawbacks of each type of methods

An ageing-aware Digital Synthesis Approach

Due to the shrinkage of CMOS technology, wear-outmechanisms such as Bias Temperature Instability (BTI) haveraised growing concerns for circuit reliability. BTI can causea threshold voltage shift in CMOS devices and consequentlyincrease circuit delay. This paper presents an ageing-aware gate-leveloptimization approach that can be used in a modernsynthesis process. It aims to optimize a circuit to give improvedlifetime reliability under given area and timing constraints. A newsensitivity metric is proposed as a function of area increase, delayreduction, degradation reduction and design constraints. Thissensitivity metric can be adjusted to select the most favourablegates in terms of circuit timing, lifetime or both. By iterativelyup-sizing the gates with the highest sensitivity, our proposedoptimization flow can meet any realizable area and timingconstraints, to give up to 3.3x lifetime improvement

Dataset for Lifetime Reliability-aware Digital Synthesis

Open data for: Duan, S., Zwolinski, M., &amp; Halak, B. (2018). Lifetime Reliability-aware Digital Synthesis. IEEE Transactions on Very Large Scale Integration (VLSI) Systems.</span