Event-driven integrated circuit having interface system

The present invention relates to an event-driven integrated circuit, comprising a sensor, an interface system and a processor. By means of the solution, events with addresses are asynchronously generated and processed. The interface system comprises a replication module, a fusion module, a secondary sampling module, a region of interest module, an event routing module, etc., which constitute a programmable daisy chain. The sensor, the interface system and the processor are coupled on a single chip by means of an adapter board, and different bare dies can be manufactured by using different processes. By means of the solution, signal loss and noise interference in the prior art can be eliminated, and the technical effects of high-speed processing of signals, smaller footprints of chips, reduced manufacturing costs, etc., are achieved, thereby solving the technical problems in the prior art of a large chip area and a low signal processing capability. In addition, by means of the smart design of the interface system, the functions and configurability of the interface system are enriched, thereby providing various advantages in terms of power consumption, functions and speed in subsequent processing

Data updating method and device, storage space setting method and device, chip and equipment

The invention discloses a data updating method, a storage space setting method and device, a chip and equipment. In order to solve the technical problems that in the prior art, the classification number of data reading layers in a neural mimicry chip is fixed, the occupied area of the chip is large, and shared storage cannot be achieved, a pulse sequence output by a pulse neural network is read through the data reading layers of a memory. The method comprises the steps of: analyzing the pulse sequence to determine a prediction type of the pulse neural network for the input data; determining a target storage address corresponding to the prediction type in a storage address sequence of a memory; and updating the pulse aggregation analysis information stored in the first storage space and the pulse counting statistical information stored in the second storage space according to the pulse sequence. Based on the technical means, the technical effects of improving the data storage and updating efficiency in the dynamic readout layer, dynamically allocating the moving average value memory, reducing the chip area, dynamically configuring the number of output classes and the like are achieved