Evaluation of persistent-mode operation in a superconducting MgB2 coil in solid nitrogen

We report the fabrication of a magnesium diboride (MgB2) coil and evaluate its persistent-mode operation in a system cooled by a cryocooler with solid nitrogen (SN2) as a cooling medium. The main purpose of SN2 was to increase enthalpy of the cold mass. For this work, an in situ processed carbon-doped MgB2 wire was used. The coil was wound on a stainless steel former in a single layer (22 turns), with an inner diameter of 109 mm and height of 20 mm without any insulation. The two ends of the coil were then joined to make a persistent-current switch to obtain the persistent-current mode. After a heat treatment, the whole coil was installed in the SN2 chamber. During operation, the resultant total circuit resistance was estimated to be \u3c7.4x10−14 Ω at 19.5 K±1.5 K, which meets the technical requirement for magnetic resonance imaging application

MIMO detection and precoding architectures

Abstract Multiple-input multiple-output (MIMO) techniques have been adopted since the third generation (3G) wireless communication standard to increase the spectral efficiency, data rate and reliability. The blessings of MIMO technologies for the baseband transceiver comes with the price of added complexity. Therefore, research on VLSI architectures for MIMO signal processing has generated a lot of interest over the past two decades. The advent of massive MIMO as a key technology for the fifth generation (5G) era also increased the interest in VLSI architectures related to MIMO communication research. In this thesis, we explored different VLSI architectures for MIMO detection and precoding algorithms. The detection and precoding are the most complex parts of a MIMO baseband transceiver. We focused on algorithm and architecture optimization and presented several VLSI architectures for MIMO detection and precoding. The thesis proposed an application specific instruction-set processor (ASIP) for a multimode small-scale MIMO detector. In a single design the detector supports minimum mean-square error (MMSE), selective spanning with fast enumeration (SSFE) and list sphere detection (LSD). In addition, a multiprocessor architecture is proposed in this thesis for a lattice reduction (LR) algorithm. A modified Lenstra-Lenstra-Lovasz (LLL) algorithm is proposed for LR to reduce the complexity of the original LLL algorithm. We also propose a massive MIMO detection algorithm based on alternating direction method of multipliers (ADMM). The algorithm is referred to as ADMM based infinity norm (ADMIN) constrained equalization. The ADMIN detection algorithm is implemented as an application-specific integrated circuit (ASIC) and for field programmable gate array (FPGA). A multimode precoder ASIP is also proposed in this thesis. In a single design, the ASIP supports norm-based scheduling, QR-decomposition, MMSE precoding and dirty paper coding (DPC) based precoding.Tiivistelmä Moni-tulo moni-lähtö (MIMO) -tekniikoita on sopeutettu kolmannen sukupolven (3G) langattomasta viestintästandardista alkaen spektritehokkuuden, tiedonsiirtonopeuden ja luotettavuuden parantamiseksi. MIMO-teknologioilla on useita hyviä puolia suhteessa peruskaistan vastaanottimeen, mutta samalla monimutkaisuus on lisääntynyt. VLSI-arkkitehtuurien tutkimus MIMO-signaalinkäsittelyssä on sen vuoksi herättänyt paljon kiinnostusta viimeisen kahden vuosikymmenen aikana. Myös MIMO:n saavuttama asema viidennen sukupolven (5G) viestintästandardin pääteknologiana on lisännyt kiinnostusta VLSI-arkkitehtuureihin MIMO-viestinnän tutkimuksessa. Tässä tutkielmassa on tutkittu erilaisia VLSI-arkkitehtuureja MIMO-signaalien tunnistus- ja esikoodausalgoritmeissa. Signaalien tunnistus ja esikoodaus ovat peruskaistaa käyttävän MIMO-vastaanottimen monimutkaisimmat osa-alueet. Tutkielmassa on keskitytty algoritmien ja arkkitehtuurien optimointiin ja esitetty useita VLSI-arkkitehtuureja MIMO-signaalien tunnistusta ja esikoodausta varten. Tutkielmassa on ehdotettu sovelluskohtaisen prosessorin (Application Specific Instruction-set Processor eli ASIP) käyttä pienen mittakaavan monimuotodetektorissa. Detektorin rakenne tukee samanaikaisesti keskineliöpoikkeaman minimointia (MMSE), SSFE (Selective Spanning with Fast Enumeration) -algoritmia ja LSD (List Sphere Detection) -algoritmia. Lisäksi tässä tutkielmassa ehdotetaan monisuoritinarkkitehtuuria hilan redusointialgoritmille (Lattice Reduction eli LR). LR-algoritmia varten ehdotetaan muokattua Lenstra-Lenstra-Lovasz (LLL) -algoritmia vähentämään alkuperäisen LLL-algoritmin monimutkaisuutta. Lisäksi MIMO-signaalien tunnistusalgoritmin perustaksi ehdotetaan vuorottelevaa kertoimien suuntaustapaa Alternating Direction Method of Multipliers eli ADMM). ADMM-perustaisesta taajuusvasteen rajoitetusta ääretön-normi-korjauksesta (infinity norm constrained equalization) käytetään nimitystä ADMIN-algoritmi. ADMIN-tunnistusalgoritmi toteutetaan sovelluskohtaisena integroituna piirinä (Application-Specific Integrated Circuit eli ASIC) ohjelmoitavaa porttimatriisia (Field Programmable Gate Array eli FPGA) varten. Lisäksi ehdotetaan ASIP-monimuotoesikooderin käyttöä. ASIP-esikooderin rakenne tukee normiperustaista aikataulutusta, QR-hajotelmaa, MMSE-esikoodausta ja likaisen paperin koodaukseen (Dirty Paper Coding eli DPC) perustuvaa esikoodausta

Concept drift detection methods for deep learning cognitive radios:a hardware perspective

Abstract Deep learning models usually assume that training dataset and target data have the same distribution. If this is not the case, model mismatch causes performance degradation when the model is used with the real data. With radio frequency (RF) measurements from real data traffic, the exact distribution of the measurements is unknown in many cases and model mismatch is unavoidable. This is known as concept drift, or model mis- specification in deep learning, which we are interested in for cognitive radio dynamic spectrum access predictions. In this paper, we present three concept drift detection methods and their corresponding very large scale integration (VLSI) circuits. The circuits are mapped on a Xilinx Virtex-7 field-programmable gate array (FPGA) and the resource utilization results are provided

A fractional sample rate converter with parallelized multiphase output:algorithm and FPGA implementation

Abstract Sample rate conversion is an essential scheme used in almost every radio design. Supporting sampling rates higher than the clock rates require parallel processing. In this paper, we propose an algorithm for a sample rate converter (SRC) with multiple parallel output phases so that the conversion ratio can be a fixed rational number. Due to the structure of the proposed algorithm, it is suitable for embedded platforms which are restricted by their clock frequency but require very high sample rates. A dual phase output variant of the proposed algorithm is simulated with a 400 MHz input signal to perform a 15/8 conversion. The test and verification of the SRC algorithm is presented with the aid of a design example. A VLSI architecture of the dual phase output SRC is implemented on a Virtex-7 field-programmable gate array (FPGA) and results are presented

ASIP design for multiuser MIMO broadcast precoding

Abstract This paper presents an application-specific instruction-set processor (ASIP) for multiuser multiple-input multiple-output (MU-MIMO) broadcast precoding. The ASIP is designed for a base station (BS) with four antennas to perform user scheduling and precoding. Transport triggered architecture (TTA) is used as the processor template and high level language is used to program the ASIP. Several special function units (SFU) are designed to accelerate norm-based greedy user scheduling and minimum-mean square error (MMSE) precoding. We also program zero forcing dirty paper coding (ZF-DPC) to demonstrate the reusability of the ASIP. A single core provides a throughput of 52.17 Mbps for MMSE precoding and takes an area of 87.53 kgates at 200 MHz on 90 nm technology

Programmable ASIPs for multimode MIMO transceiver

Abstract Application specific instruction-set processors (ASIP) are a programmable and flexible alternative of traditional finite state machine (FSM) controlled register-transfer level (RTL) designs for multimode basedband systems. In this paper, we present two ASIPs for small scale multiple-input multiple-output (MIMO) wireless communication systems that demonstrate the soundness and effectiveness of ASIPs for this type of applications. The first ASIP is programmed with multiple MIMO symbol detection algorithms for 4 × 4 systems. The supported detection algorithms are minimum mean-square error (MMSE), two variants of the selective spanning with fast enumeration (SSFE) and K-best list sphere detection (LSD). The second ASIP supports MMSE and zero-forcing dirty paper coding (ZF-DPC) algorithms for a base station (BS) with 4 antennas and for 4 users. Both ASIPs are based on transport triggered architecture (TTA) and are programmed with a retargetable compiler with high level language to meet the time-to-market requirements. The detection and precoding algorithms can be switched in the respective ASIPs based on the error-rate requirements. Depending on the algorithms, MIMO detection ASIP delivers 6.16—66.66 Mbps throughput at a clock frequency of 200 MHz on 90 nm technology. The precoder ASIP provides a throughput of 52.17 and 51.95 Mbps for MMSE and ZF-DPC precoding respectively at a clock frequency of 210 MHz on 90 nm technology

Deep unfolding of Chebyshev accelerated iterative method for massive MIMO detection

Abstract The zero-forcing (ZF) and minimum mean square error (MMSE) based detectors can approach optimal performance in the uplink of massive multiple-input multiple-output (MIMO) systems. However, they require inverting a matrix whose complexity is cubic in relation to the matrix dimension. This can lead to the high computational effort, especially in massive MIMO systems. To mitigate this, several iterative methods have been proposed in the literature. In this paper, we consider accelerated Chebyshev SOR (AC-SOR) and accelerated Chebyshev AOR (AC-AOR) algorithms, which improve the detection performance of conventional Successive Over-Relaxation (SOR) and Accelerated Over-Relaxation (AOR) methods, respectively. Additionally, we propose using a deep unfolding network (DUN) to optimize the parameters of the iterative AC-SOR and AC-AOR algorithms, leading to the AC-AORNet and AC-SORNet methods, respectively. The proposed DUN-based method leads to significant performance improvements compared to conventional iterative detectors for various massive MIMO channels. The results demonstrate that the AC-AORNet and AC-SORNet are effective, outperforming other state-of-the-art algorithms. Furthermore, they are highly effective, particularly for high-order modulations such as 256-QAM (Quadrature Amplitude Modulation). Moreover, the proposed AC-AORNet and AC-SORNet require almost the same number of computations as AC-AOR and AC-SOR methods, respectively, since the use of deep unfolding has a negligible impact on the system’s detection complexity. Furthermore, the proposed DUN features a fast and stable training scheme due to its smaller number of trainable parameters

Massive MIMO detection techniques:a survey

Abstract Massive multiple-input multiple-output (MIMO) is a key technology to meet the user demands in performance and quality of services (QoS) for next generation communication systems. Due to a large number of antennas and radio frequency (RF) chains, complexity of the symbol detectors increased rapidly in a massive MIMO uplink receiver. Thus, the research to find the perfect massive MIMO detection algorithm with optimal performance and low complexity has gained a lot of attention during the past decade. A plethora of massive MIMO detection algorithms has been proposed in the literature. The aim of this paper is to provide insights on such algorithms to a generalist of wireless communications. We garner the massive MIMO detection algorithms and classify them so that a reader can find a distinction between different algorithms from a wider range of solutions. We present optimal and near-optimal detection principles specifically designed for the massive MIMO system such as detectors based on a local search, belief propagation and box detection. In addition, we cover detectors based on approximate inversion, which has gained popularity among the VLSI signal processing community due to their deterministic dataflow and low complexity. We also briefly explore several nonlinear small-scale MIMO (2—4 antenna receivers) detectors and their applicability in the massive MIMO context. In addition, we present recent advances of detection algorithms which are mostly based on machine learning or sparsity based algorithms. In each section, we also mention the related implementations of the detectors. A discussion of the pros and cons of each detector is provided

FPGA implementation of stair matrix based massive MIMO detection

Abstract Approximate matrix inversion based methods is widely used for linear massive multiple-input multiple-output (MIMO) received symbol vector detection. Such detectors typically utilize the diagonally dominant channel matrix of a massive MIMO system. Instead of diagonal matrix, a stair matrix can be utilized to improve the error-rate performance of a massive MIMO detector. In this paper, we present very large-scale integration (VLSI) architecture and field programmable gate array (FPGA) implementation of a stair matrix based iterative detection algorithm. The architecture supports a base station with 128 antennas, 8 users with single antenna, and 256 quadrature amplitude modulation (QAM). The stair matrix based detector can deliver a 142.34 Mbps data rate and reach a clock frequency of 258 MHz in a Xilinx Virtex -7FPGA. The detector provides superior error-rate performance and higher scaled throughput than most contemporary massive MIMO detectors

ADMM-based infinity-norm detection for massive MIMO:algorithm and VLSI architecture

Abstract In this article, we propose a novel data detection algorithm and a corresponding VLSI design for massive multiuser (MU) multiple-input–multiple-output (MIMO) wireless systems. Our algorithm uses alternating direction method of multipliers (ADMM)-based infinity-norm-constrained equalization and is called ADMIN. ADMIN is an iterative algorithm that outperforms linear detectors by a large margin when the ratio between the numbers of base-station (BS) and user antennas is small. In the first iteration, ADMIN computes the linear minimum mean-square error (MMSE) solution, which is sufficient when the ratio between the numbers of BS and user antennas is large. We develop time-shared and iterative VLSI architectures for LDL-decomposition-based soft-output ADMIN supporting 16- and 32-user systems. We present application-specific integrated circuit (ASIC) designs for 16–64 antenna base stations in 28-nm CMOS that supports up to 64 quadrature amplitude modulation (QAM). The 16-user ADMIN ASIC achieves 303 Mb/s while dissipating 85 mW. The 32-user ADMIN ASIC achieves 287 and 241 Mb/s while dissipating 121 and 135 mW for 32 and 64 BS antennas, respectively. ADMIN has also been implemented on a Xilinx Virtex-7 field-programmable gate array (FPGA) and is compared with state-of-the-art massive MIMO data detectors