Toward Solving Multichannel RF-SoC Integration Issues Through Digital Fractional Division

In modern RF system on chips (SoCs), the digital content consumes up to 85% of the IC chip area. The recent push to integrate multiple RF-SoC cores is met with heavy resistance by the remaining RF/analog circuitry, which creates numerous strong aggressors and weak victims leading to RF performance degradation. A key such mechanism is injection pulling through parasitic coupling between various LC-tank oscillators as well as between them and strong transmitter (TX) outputs. Any static or dynamic frequency proximity between aggressors (i.e., oscillators and TX outputs) and victims (i.e., oscillators) that share the same die causes injection pulling, which produces unwanted spurs and/or modulation distortion. In this paper, we propose and demonstrate a new frequency planning technique of a multicore TX where each LC -tank oscillator is separated from other aggressors beyond its pulling range. This is done by breaking the integer harmonic frequency relationship of victims/aggressors within and between the RF transmission channels using digital fractional divider based on a phase rotation. Each oscillator's center frequency can be fractionally separated by ~28% but, at the same time, both producing closely spaced frequencies at the phase rotator outputs. The injection-pulling spurs are so far away that they are insignificantly small (-80 dBc) and coincide with the second harmonic of the carrier. This method is experimentally verified in a two-channel system in 65-nm digital CMOS, each channel comprising a high-swing class-C oscillator, frequency divider, and phase rotator.European Research Counci

Versatile DAC-less successive approximation ADC architecture for medium speed data acquisition

Implementation of the DAC is usually the bottleneck in designing a SAR ADC. Here an innovative DAC-less SAR (DLSAR) ADC architecture is presented which alleviates some drawbacks of the conventional SAR counterpart. The proposed DLSAR binary search algorithm is comprised of two arithmetic operations of division-by-two and subtraction to emulate the DAC function. The hardware of the DLSAR ADC is implemented using ordinary circuit building blocks of a SAR ADC but with less complexity and more robustness against PVT variations as DAC is removed. The developed DLSAR architecture is versatile so that the converter hardware could be readily reconfigured for different sampling rates and resolutions. Based on post-layout simulations in 0.18 μm CMOS process, the designed 8-bit DLSAR ADC consumes 150 μW of power at 2 MS/s including the asynchronous control logic circuit. The SFDR of the converter is up to 62 dB and the ENOB reaches 7.8 bits while it remains above 7.5 bits across most PVT corners without calibration. Also, by reconfiguring the DLSAR ADC to 9-bit resolution at 1 MS/s, the ENOB is generally around 8.2 bits achieving a scaled figure-of-merit (SFoM) better than 3.0 Ç/c-s.Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.Bio-Electronic