Timing Recovery By Symbol Spaced and Fractionally Spaced Equalizers

This paper presents a study of the digital timing recovery for high speed QAM receivers based on the symbol spaced and fractionally spaced equalizers (FSE). The aim of the investigation is to fix the intersymbol interference (ISI) caused by the clock phase error and frequency error between the transmitter and the receiver by the complex adaptive equalizer, hereby eliminating the interpolator and the timing error detector (TED). By this approach it is intended to improve the performance and the cost-effectiveness of the VDSL receiver chip. Both the blind equalization and the adaptation with the use of the training sequences are discussed. The model of the introduced phase error is described. The influence of the phase error on the signal to be detected is studied in the time and the frequency domain. During the investigation of the equalizers' behaviour two basic operation conditions of the receiver are considered. First, the received signal is corrupted by the constant phase error. Thi..

Hardware reuse at the behavioral level

Standard interfaces for hardware reuse are currently de ned at the structural level. In contrast to this, our contribution de nes the reuse interface at the behavioral registertransfer (RT) level. This promotes direct reuse of functionality and avoids the integration problems of structural reuse. We present an object oriented reuse interface in C++ and show the use of it within two real-life designs.

Design Space Exploration of All-Digital Symbol Timing Adjustment Architectures

In this contribution, a design space exploration of the various possible schemes for alldigital symbol timing adjustment of QAM signals is made. The exploration is guided by both performance degradation and implementation cost considerations. The BER performance degradation is obtained using a quasianalytic simulation approach, while the implementation cost is estimated by high level digital circuit synthesis. The results show that a good performance/implementation tradeoff is obtained by using baseband interpolation with an oversampling factor of three and adequate compensation. This timing adjustment circuit is now being applied in the design of a digital downstream CATV QAM receiver. 1 Introduction Currently, digital modems for broadband communication over coaxial or twisted pair access networks are of major interest. The high speed requirements together with a need for integration call for an all-digital solution, where all synchronization loops are implemented digitally on-chip...

A 10 Mbit/s Upstream Cable Modem with Automatic EqualizationPatrick Schaumont Radim Cmar Serge Vernalde Marc Engels

A fully digital QAM16 burst receiver ASIC is presented. The BO4 receiver demodulates at 10 Mbit/s and uses an advanced signal processing architecture that performs perburst automatic equalization. It is a critical building block in a broadband access system for HFC networks. The chip was designed using a C++ based flow and is implemented as a 80 Kgate 0.7u CMOS standard cell design. 1 Introduction The widespread use of Internet is opening a pathway to emerging multimedia consumer networks and applications. These require a broadband data communications link to be established in the access network that connects the consumer to a core service network. The hybrid fiber-coax (HFC) access network that is currently in use for cable TV, is considered as an attractive candidate [4]. We have developed a chip that is embedded in an HFC head-end and that demodulates data transmitted from the consumer set-top. This chip is a fully digital burst receiver, characterized as shown in table 1. The chip..