Mindfulness-based supportive therapy on reducing suffering in patients with advanced cancer: randomised controlled trial

Objectives Suffering is common among patients with advanced cancer. The practice of mindfulness during patient care can potentially reduce suffering. We aimed to examine the efficacy of mindfulness-based supportive therapy (MBST) on reducing suffering in patients with advanced cancer. Methods We conducted a parallel-group, single-blinded, randomised controlled trial at the University of Malaya Medical Centre, Malaysia. Seventy-three patients with advanced cancer with an overall suffering score ≥4/10 based on the Suffering Pictogram were recruited and randomly assigned into either the MBST group (n=34) or the control group (n=39). Results There was a statistically significant reduction in the overall suffering score in the MBST group compared with the control group (U=432.5, median1 =−2.0, median2 =−1.0, z=−2.645, p=0.008). There was also significant improvement in the total Hospital Anxiety and Depression Scale score (U=483.5, median1 =−4.0, median2 =−3.0, z=−1.994, p=0.046), and the total Functional Assessment of Chronic Illness Therapy-Spiritual Well-Being score (U=252.0, median1 =+14.5, median2 =+5.0, z=−4.549, p=0.000) in the MBST group compared with the control group. Conclusions The results provided evidence that the practice of MBST during patient care could promote positive psychosocial outcome

Novel Architecture for Loop Acceleration:ACase Study Abstract

In this paper, we show a novel approach to accelerate loops by tightly coupling a coprocessor to an ASIP. Latency hiding is used to exploit the parallelism available in this architecture. To illustrate the advantages of this approach, we investigate a JPEG encoding algorithm and accelerate one of its loop by implementing it in a coprocessor. We contrast the acceleration by implementing the critical segment as two different coprocessors and a set of customized instructions. The two different coprocessor approaches are: a high-level synthesis (HLS) approach; and a custom coprocessor approach. The HLS approach provides a faster method of generating coprocessors. We show that a loop performance improvement of 2.57x is achieved using the custom coprocessor approach, compared to 1.58x for the HLS approach and 1.33x for the customized instruction approach compared with just the main processor. Respective energy savings within the loop are 57%, 28

Design Methodology for Pipelined Heterogeneous Multiprocessor System

Multiprocessor SoC systems have led to the increasing use of parallel hardware along with the associated software. These approaches have included coprocessor, homogeneous processor (e.g. SMP) and application specific architectures (i.e. DSP, ASIC). ASIPs have emerged as a viable alternative to conventional processing entities (PEs) due to its configurability and programmability. In this work, we introduce a heterogeneous multi-processor system using ASIPs as processing entities in a pipeline configuration. A streaming application is taken and manually broken into a series of algorithmic stages (each of which make up a stage in a pipeline). We formulate the problem of mapping each algorithmic stage in the system to an ASIP configuration, and propose a heuristic to efficiently search the design space for a pipeline-based multi ASIP system. We have implemented the proposed heterogeneous multiprocessor methodology using a commercial extensible processor (Xtensa LX from Tensilica Inc.). We have evaluated our system by creating two benchmarks (MP3 and JPEG encoders) which are mapped to our proposed design platform. Our multiprocessor design provided a performance improvement of at least 4.11X (JPEG) and 3.36X (MP3) compared to the single processor design. The minimum cost obtained through our heuristic was within 5.47 % and 5.74 % of the best possible values for JPEG and MP3 benchmarks respectively

Ensuring Secure Program Execution in Multiprocessor Embedded Systems: A Case Study

Multiprocessor SoCs are increasingly deployed in embedded systems with little or no security features built in. Code Injection attacks are one of the most commonly encountered security threats. Most solutions to this problem in the single processor domain are purely software based and have high overheads. A few hardware solutions have been provided for the single processor case, which significantly reduce overheads. In this paper, for the first time, we propose a methodology addressing code injection attacks in a multiprocessor domain. A dedicated security (monitor) processor is used to oversee the application at runtime. Each processor communicates with the monitor processor through a FIFO queue, and is continuously checked. Static analysis of program map and timing profile are used to obtain program information at compile time, which is utilized by the monitor processor at runtime. This information is encrypted using a secure key and stored in the monitor processor. A copy of this secure key is built into the processor’s hardware and is used for decryption by the monitor processor. Each basic block of the program is also instrumented with security information that uniquely identifies itself at runtime. The information from static analysis thus allows the monitor processor to supervise the proceedings on each processor at runtime. Our approach uses a combination of hardware and software techniques to keep overheads to a minimum. We implemented our methodology on a commercial extensible processor (Xtensa LX). Our approach successfully detects the execution of injected code when tested on a JPEG multiprocessor benchmark. The results show a small increase of 6.6 % in application processors ’ runtime (clock cycle count) and 35.2 % in code size for the JPEG encoder benchmark

Team 7: Applying Automated Red Teaming in a Maritime Scenario

from Scythe : Proceedings and Bulletin of the International Data Farming Community, Issue 2 Workshop 14With shipping at the heart of the global economy, maritime security is required to ensure freedom of the seas and to facilitate freedom of navigation and commerce. It is therefore important for nations to stand united and share in the responsibility for maintaining maritime security, when faced with an array of threats from the terrorists and criminals. This study will focus on one aspect of the maritime security - key installation (KINs) protection

Rapid Embedded Hardware/Software System Generation

This paper presents an RTL generation scheme for a SimpleScalar / PISA Instruction set architecture with system calls to implement C programs. The scheme utilizes ASIPmeister, a processor generation tool. The RTL generated is available for download. The second part of the paper shows a method of reducing the PISA instruction set and generating a processor for a given application. This reduction and generation can be performed within an hour, making this one of the fastest methods of generating an application specific processor. For five benchmark applications, we show that on average, processor size can be reduced by 30 % , energy consumed reduced by 24%, and performance improved by 24%. 1

ADAPT : architectural and design exploration for application specific instruction-set processor technologies

This thesis presents design automation methodologies for extensible processor platforms in application specific domains. The work presents first a single processor approach for customization; a methodology that can rapidly create different processor configurations by the removal of unused instructions sets from the architecture. A profile directed approach is used to identify frequently used instructions and to eliminate unused opcodes from the available instruction pool.A coprocessor approach is next explored to create an SoC (System-on-Chip) to speedup the application while reducing energy consumption. Loops in applications are identified and accelerated by tightly coupling a coprocessor to an ASIP (Application Specific Instruction-set Processor). Latency hiding is used to exploit the parallelism provided by this architecture. A case study has been performed on a JPEG encoding algorithm; comparing two different coprocessor approaches: a high-level synthesis approach and our custom coprocessor approach.The thesis concludes by introducing a heterogenous multi-processor system using ASIPs as processing entities in a pipeline configuration. The problem of mapping each algorithmic stage in the system to an ASIP configuration is formulated. We proposed an estimation technique to calculate runtimes of the configured multiprocessor system without running cycle-accurate simulations, which could take a significant amount of time. We present two heuristics to efficiently search the design space of a pipeline-based multi ASIP system and compare the results against an exhaustive approach.In our first approach, we show that, on average, processor size can be reduced by 30%, energy consumption by 24%, while performance is improved by 24%. In the coprocessor approach, compared with the use of a main processor alone, a loop performance improvement of 2.57x is achieved using the custom coprocessor approach, as against 1.58x for the high level synthesis method, and 1.33x for the customized instruction approach. Energy savings are 57%, 28% and 19%, respectively. Our multiprocessor design provides a performance improvement of at least 4.03x for JPEG and 3.31x for MP3, for a single processor design system. The minimum cost obtained using our heuristic was within 0.43% and 0.29% of the optimum values for the JPEG and MP3 benchmarks respectively