Virtual Machine Support for Many-Core Architectures: Decoupling Abstract from Concrete Concurrency Models

The upcoming many-core architectures require software developers to exploit concurrency to utilize available computational power. Today's high-level language virtual machines (VMs), which are a cornerstone of software development, do not provide sufficient abstraction for concurrency concepts. We analyze concrete and abstract concurrency models and identify the challenges they impose for VMs. To provide sufficient concurrency support in VMs, we propose to integrate concurrency operations into VM instruction sets. Since there will always be VMs optimized for special purposes, our goal is to develop a methodology to design instruction sets with concurrency support. Therefore, we also propose a list of trade-offs that have to be investigated to advise the design of such instruction sets. As a first experiment, we implemented one instruction set extension for shared memory and one for non-shared memory concurrency. From our experimental results, we derived a list of requirements for a full-grown experimental environment for further research

Silicon Nanomaterials for Li-ion Energy Storage Microsystems

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Thin-film fully-depleted SOI CMOS technology devices and circuits for LVLP analog/digital/microwave applications

This paper demonstrates that fully-depleted silicon-on-insulator technology offers unique opportunities in the field of low-voltage, low-power CMOS circuits, allowing for the mixed fabrication and operation under low supply voltage of analog, digital and microwave components with properties significantly superior to those obtained on bulk CMO

Improving Dielectric Constant and Residual Stress in Metal-Insulator-Metal Capacitors Using Different Stacked Thick Dielectric Materials

This study aims to analyze and compare the characteristics of Metal-Insulator-Metal (MIM) capacitors, focusing on the effect of the stacking selection of thick dielectric materials, for future applications requiring robustness to high voltages and temperatures. The 300 nm-thick dielectric stacks under investigation include SiO 2 and Si 3 N 4 materials deposited using plasma-enhanced chemical vapor deposition (PECVD) at a high temperature (300°C), as well as Al 2 O 3 deposited through reactive sputtering at room temperature. The experimental results presented in this work highlight the importance of the stacking choice of these dielectric materials for minimizing the residual stress and the temperature coefficient of capacitance (TCC) and enhancing the overall dielectric constant. These factors contribute to achieving increased capacitance density, with mechanical and electrical resistance to harsh conditions