Graphene and Beyond: Recent Advances in Two-Dimensional Materials Synthesis, Properties, and Devices

Since the isolation of graphene in 2004, two-dimensional (2D) materials research has rapidly evolved into an entire subdiscipline in the physical sciences with a wide range of emergent applications. The unique 2D structure offers an open canvas to tailor and functionalize 2D materials through layer number, defects, morphology, moir\ue9 pattern, strain, and other control knobs. Through this review, we aim to highlight the most recent discoveries in the following topics: theory-guided synthesis for enhanced control of 2D morphologies, quality, yield, as well as insights toward novel 2D materials; defect engineering to control and understand the role of various defects, including in situ and ex situ methods; and properties and applications that are related to moir\ue9 engineering, strain engineering, and artificial intelligence. Finally, we also provide our perspective on the challenges and opportunities in this fascinating field

Logic Locking of Integrated Circuits Enabled by Nanoscale MoS₂‑Based Memtransistors

With an ever-increasing globalization of the semiconductor chip manufacturing supply chain coupled with soaring complexity of modern-day integrated circuits (ICs), intellectual property (IP) piracy, reverse engineering, counterfeiting, and hardware trojan insertion have emerged as severe threats that have compromised the security of critical hardware components. Logic locking (LL) is an IP protection technique that can mitigate these threats by locking a given IC with a secret key. Earlier LL demonstrations based on traditional silicon complementary metal-oxide-semiconductor (CMOS) technology and emerging memristors require significant hardware investment in the form of additional input gates and extensive CMOS peripherals, rendering them area- and energy-inefficient. In this article, we demonstrate multiple two-dimensional (2D) nanoscale memtransistor-based programmable logic gates such as AND, NAND, OR, XOR, and NOT gates, each of which can be locked/unlocked without requiring peripherals and at minuscule energy expenditure (<1 pJ). We also show that SAT-solver is unsuccessful in breaking into any of the ISCAS’85 benchmark circuits that utilize our LL scheme. The massive resilience to SAT-attack is attributed to the prowess of programmable 2D memtransistors which enable device-level LL of all the gates in each of the benchmark circuits. Given that 2D transistors are drawing increasing attention of chip manufacturing corporations like Intel, TSMC, etc., to replace and/or augment silicon at aggressively scaled technology nodes, our demonstration of area- and energy-efficient LL can be considered as a step toward the realization of secure ICs enabled by 2D nanoscale memtransistors