A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC

This paper presents the design of a 9-bit, Two-Step Time-to-Digital Converter (TDC) in 65 nm CMOS for the application in a time-mode ADC. The proposed TDC uses body-biasing in the fine TDC to obtain the resolution of the entire TDC, which is simulated to be 1.08 ps. With a dynamic range of 555 ps, the maximum conversion time between START and the availability of results is 2.7 ns. The proposed TDC consumes 0.667 mW at 200 MHz, with a FoM of 0.0065 pJ/conversion. The DNL and INL are simulated to be -0.097/0.2 LSB and -0.12/0.41 LSB respectively

An inductorless wideband balun-LNA in 65nm CMOS with balanced output

An inductorless LNA with active balun is designed for multi-standard radio applications between 100MHz and 6GHz. It exploits a combination of a common gate stage and a common source stage with replica biasing to maximize balanced operation. The NF is designed to be around 3dB by using the noise canceling technique. Its best performance is achieved between 300MHz to 3.5GHz with gain and phase errors below 0.3dB and ± 2degrees, 15dB gain, S11<-14dB, IIP3 = OdBm and IIP2 higher than +2OdBm at a total power consumption of 21mW. The circuit is fabricated in a baseline 65nm CMOS process, with an active area of only 0.01mm2. The circuit simultaneously achieves impedance matching, noise canceling and a well balanced output

Characterization of the magnetization reversal of perpendicular Nanomagnetic Logic clocked in the ns-range

We have investigated the magnetization reversal of fabricated Co/Pt nanomagnets with perpendicular anisotropy within a wide range of magnetic field pulse widths. This experiment covers the pulse lengths from 700 ms to 20 ns. We observed that the commonly used Arrhenius model fits very well the experimental data with a single parameter set for pulse times above 100 ns (tp > 100 ns). However, below 100 ns (tp < 100 ns), a steep increase of the switching field amplitude is observed and the deviation from the Arrhenius model becomes unacceptable. For short pulse times the model can be adjusted by the reversal time term for the dynamic switching field which is only dependent on the pulse amplitude and not on temperature anymore. Precise modeling of the magnetization reversal in the sub-100 ns-range is crucially important to ensure reliable operation in the favored GHz-range as well as to explore and design new kinds of Nanomagnetic Logic circuits and architectures

1-Bit Full Adder in Perpendicular Nanomagnetic Logic using a Novel 5-Input Majority Gate

In this paper, we show that perpendicular Nanomagnetic Logic (pNML) is particularly suitable to realize threshold logic gate (TLG)-based circuits. Exemplarily, a 1-bit full adder circuit using a novel 5-input majority gate based on TLGs is experimentally demonstrated. The theory of pNML and its extension by TLGs is introduced, illustrating the great benefit of pNML. Majority gates based on coupling field superposition enable weighting each input by its geometry and distance to the output. Only 5 magnets, combined in two logic gates with a footprint of 1:95 µm2 and powered by a perpendicular clocking field, are required for operation. MFM and magneto-optical measurements demonstrate the functionality of the fabricated structure. Experimental results substantiate the feasibility and the benefits of the combination of threshold logic with pNML