9 research outputs found
A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI
We present a low-power, energy efficient 32-bit RISC-V microprocessor unit
(MCU) in 22 nm FD-SOI. It achieves ultra-low leakage,even at high temperatures,
by using an adaptive reverse body biasing aware sign-off approach, a low-power
optimized physical implementation, and custom SRAM macros with retention mode.
We demonstrate the robustness of the chip with measurements over the full
industrial temperature range, from -40 {\deg}C to 125 {\deg}C. Our results
match the state of the art (SOTA) with 4.8 uW / MHz at 50 MHz in active mode
and surpass the SOTA in ultra-low-power retention mode.Comment: accepted at ISOCC 202