Role of Non-Idealities in III-V/Si and All III-V Tunnel Field Effect Transistors

Energy scaling of integrated circuits has hit a roadblock as the operating voltage of the MOSFET-based solid state switches has attained a minimum possible value. The thermionic emission mechanism, which governs the switching of the Metal-Oxide Semiconductor Field Effect Transistors (MOSFETs), does not allow to achieve subthreshold swing below 60 mV/decade at room temperature, thus establishing a lower limit on the operating voltage. Tunnel Field Effect Transistors (TFETs) which operate on the principle of field modulation of Band-to-band Tunneling (BTBT) can deliver a subthreshold swing less than 60 mV/dec. Therefore, TFETs are considered as a potential candidate to replace MOSFETs as solid-state switches to achieve further scaling of the supply voltage. However, the swing of a TFET is degraded by non-idealities such as traps, band tails, interface roughness, etc., which are inevitably present. To understand the effect of the non-idealities on the TFETs, physics-based models have been developed in this work and implemented in the Technology Computer Aided Design (TCAD) simulator Synopsys Sentaurus Device. Simulations show that channel quantization reduces the on-current of the TFET which is confirmed by comparison with the experimental transfer characteristics of InAs/Si TFETs. Also, interface roughness and band tails are found to degrade the swing. TCAD analysis of experimental InAs/Si and all-III-V TFETs has confirmed that, maximum degradation of the swing results from the traps at the hetero-interface and the oxide interface. Our simulation set-up has achieved good agreement with the experimentally obtained temperature dependent as well as VDS dependent transfer characteristics which confirms reliability of the set-up. Using this set-up, we have shown that, scaling of the nanowire diameter below 20nm and alignment of the gate with InAs/Si hetero-interface enables InAs/Si TFETs to deliver sub-60mV/dec swing even in the presence of traps. Additionally, ab-initio modeling is performed to better understand the origin of traps at InAs/Si interface. It reveals that dangling bonds on As atoms at the interface are primarily responsible for the high Dit

Tunneling between density-of-state tails: Theory and effect on Esaki diodes

A model for tunneling between conduction and valence band tail states in semiconductors is developed. Localized, lifetime-broadened wave functions originally proposed by Vinogradov [Fiz. Tverd. Tela 13, 3266 (1971)] facilitate the derivation of the microscopic transition rate in a homogeneous electric field of arbitrary orientation. A compact analytical form of the average macroscopic tunnel generation rate is approximately calculated assuming that the Gaussian or exponential band tail represents a ladder of closely spaced single-level densities of states. A fully analytical form yields insight into key quantities like the effective tunnel barrier, the tunneling mass, and the pre-exponential factor in comparison to band-to-band tunneling. Tail-to-tail, tail-to-band, and band-to-band tunneling rates are compared against each other over a broad range of field strengths and characteristic tail energies. The numerical implementation of the model into a commercial device simulator accounts for the inhomogeneous field in pn-junctions and excludes invalid tunnel paths. In the application to a fully characterized InGaAs pin-Esaki diode, all physical processes and parameters that might affect the IV-characteristics are carefully investigated. The value of the bandgap of In0.53Ga0.47As as a function of density, doping, and temperature is revised. It is shown that tail-induced tunneling cannot explain the strong measured valley current of the diode. Besides band-to-band tunneling, zero- and multi-phonon defect-assisted tunneling are the physical mechanisms that allow to reproduce the entire forward characteristics. Whereas tail-to-band tunneling becomes only visible for very large values of the characteristic tail energy in the heavily doped regions, tail-to-tail tunneling remains a completely negligible process.ISSN:0021-8979ISSN:1089-755

Trap-Tolerant Device Geometry for InAs/Si pTFETs

ISSN:0741-3106ISSN:1558-056

Enhance learning experience using technology in class

Majority of the students now have access to portable devices that can provide countless information at their fingertips through various resources such as learning games and interactive applications. These resources allow immediate communication and interaction between students and instructors. In this paper, we study the effectiveness of using these resources in lectures on students’ academic performance and their level of understanding of the lecture topic.  A survey was carried out for students, who have taken statistics courses at the University of Toronto, to analyze various factors of using technology in class. The results of the survey showed that a significant portion of students gained a deeper level of understanding using technology in class, thus allowing us to take advantage of technology in class to create a more immersive learning environment for students than traditional methods

Enhance learning experience using technology in class

Majority of the students now have access to portable devices that can provide countless information at their fingertips through various resources such as learning games and interactive applications. These resources allow immediate communication and interaction between students and instructors. In this study we measured students’ perception of the effectiveness of using technological tools in lectures on their academic performance and their level of understanding of the course topic. Students, who have taken statistics courses at the University of Toronto completed a survey that identified variables connected to their perception of using technology in class and the ways in which, in turn, their learning experiences were enhanced. The results of the survey showed that a significant portion of students perceived that they gained a deeper level of understanding of lecture contents when technology was used in class. Thus, based on the results of our study, we recommend that instructors take advantage of using technology in their class in order to create a more immersive learning environment for their students than using traditional instructional methodsPeer Reviewe

Density functional theory based analysis of the origin of traps at the InAs/Si hetero-interface

ISSN:0003-6951ISSN:1077-311

Impact of Non-idealities on the Performance of InAs/(In)GaAsSb/GaSb Tunnel FETs

Measured InGaAsSb/InAs nanowire TFETs showing both, sub-60mV/dec slope and high ON-current, are simulated using calibrated TCAD. The focus is laid on the impact of non-idealities, such as hetero-interface traps, oxide-interface traps, and bulk traps on device characteristics. Simulated temperature-dependent transfer curves are in good agreement with the measured data which validates the simulation set-up. It is found that trap-assisted tunneling involving bulk traps adjacent to the hetero-junction is primarily responsible for the degradation of the swing. Due to the small diameter of the nanowire, trap-assisted tunneling is inhibited at the InAs/oxide interface. Still, oxide interface traps reduce the electrostatic coupling between gate and channel, which further increases the swing. The TCAD analysis correctly predicts the negative transconductance observed at high gate bias. If the same simulation set-up is used to study the effect of gate alignment, a significant improvement of both ON-current and swing is found