Atomistic Approach to Alloy Scattering in Si(1-x)Ge(x)

SiGe alloy scattering is of significant importance with the introduction of strained layers and SiGe channels into complementary metal-oxide semiconductor technology. However, alloy scattering has till now been treated in an empirical fashion with a fitting parameter. We present a theoretical model within the atomistic tight-binding representation for treating alloy scattering in SiGe. This approach puts the scattering model on a solid atomistic footing with physical insights. The approach is shown to inherently capture the bulk alloy scattering potential parameters for both n-type and p-typecarriers and matches experimental mobility data

Engineering Nanowire n-MOSFETs at Lg < 8 nm

As metal-oxide-semiconductor field-effect transistors (MOSFET) channel lengths (Lg) are scaled to lengths shorter than Lg<8 nm source-drain tunneling starts to become a major performance limiting factor. In this scenario a heavier transport mass can be used to limit source-drain (S-D) tunneling. Taking InAs and Si as examples, it is shown that different heavier transport masses can be engineered using strain and crystal orientation engineering. Full-band extended device atomistic quantum transport simulations are performed for nanowire MOSFETs at Lg<8 nm in both ballistic and incoherent scattering regimes. In conclusion, a heavier transport mass can indeed be advantageous in improving ON state currents in ultra scaled nanowire MOSFETs.Comment: 6 pages, 7 figures, journa

Interface Trap Density Metrology of state-of-the-art undoped Si n-FinFETs

The presence of interface states at the MOS interface is a well-known cause of device degradation. This is particularly true for ultra-scaled FinFET geometries where the presence of a few traps can strongly influence device behavior. Typical methods for interface trap density (Dit) measurements are not performed on ultimate devices, but on custom designed structures. We present the first set of methods that allow direct estimation of Dit in state-of-the-art FinFETs, addressing a critical industry need.Comment: 9 pages, 4 figures, *G.C.T. and A.P. contributed equally to this wor

Interface trap density metrology from sub-threshold transport in highly scaled undoped Si n-FinFETs

Channel conductance measurements can be used as a tool to study thermally activated electron transport in the sub-threshold region of state-of-art FinFETs. Together with theoretical Tight-Binding (TB) calculations, this technique can be used to understand the evolution of source-to-channel barrier height (Eb) and of active channel area (S) with gate bias (Vgs). The quantitative difference between experimental and theoretical values that we observe can be attributed to the interface traps present in these FinFETs. Therefore, based on the difference between measured and calculated values of (i) S and (ii) |dEb/dVgs| (channel to gate coupling), two new methods of interface trap density (Dit) metrology are outlined. These two methods are shown to be very consistent and reliable, thereby opening new ways of analyzing in situ state-of-the-art multi-gate FETs down to the few nm width limit. Furthermore, theoretical investigation of the spatial current density reveal volume inversion in thinner FinFETs near the threshold voltage.Comment: 12 figures, 13 pages, Submitted to Journal of Applied Physic

Observation of 1D Behavior in Si Nanowires: Toward High-Performance TFETs

This article provides experimental evidence of one-dimensional behavior of silicon (Si) nanowires (NWs) at low-temperature through both transfer (Id−VG) and capaci- tance−voltage characteristics. For the first time, operation of Si NWs in the quantum capacitance limit (QCL) is experimentally demonstrated and quantitatively analyzed. This is of relevance since working in the QCL may allow, e.g., tunneling field-effect transistors (TFETs) to achieve higher on-state currents (Ion) and larger on-/off-state current ratios (Ion/Ioff), thus addressing one of the most severe limitations of TFETs. Comparison of the experimental data with simulations finds excellent agreement using a simple capacitor model

Physics and simulation study of nanoscale electronic devices

Silicon based CMOS technology has seen continuous scaling of device dimensions for past three decades. There is a lot of focus on incorporating different high mobility channel materials and new device architectures for post-Si CMOS logic technology, making it a multifaceted problem. In this thesis some of the multiple challenges concerning new CMOS technologies are addressed. High carrier mobility alloyed channel materials like SiGe and InGaAs suffer from scattering due to disorder called, alloy scattering. The current theory of alloy scattering present in literature/text books can be called rudimentary at the best due to lack of a strong theoretical foundation and/or use of fitting parameters to explain experimental measurements. We present a new atomistic approach based on tight-binding parameters to understanding the alloy disorder. Using this approach we are able to provide new insights into the theory of alloy scattering and explain the experimental measurements in bulk SiGe and InGaAs that were till now based on just fitting parameters. With an updated understanding of alloy scattering, hole mobility in SiGe nanowires is calculated using a linearized Boltzmann formalism. Bulk Ge exhibits high hole mobility makeing it ideal for PMOS devices. Nano patterning of Ge/SiGe leads to Ge nanofins with both uniaxial and biaxial strain components, making it a device architecture design problem. Fully atomistic simulations involving molecular dynamics (ReaxFF force field) based relaxation for strain relaxation; tight-binding based bandstructure calculations and a linearized Boltzmann transport model for mobility calculations are performed. Final phonon mobility calculations reveal nearly 3.5 X improvements compared to biaxial strained Ge in Ge nanofins with width reduction. High electron mobility III--V\u27s are projected to be a material of choice for post-Si NMOS. These low electron mass materials suffer from the \u27DOS bottleneck\u27 issue. Transistor designs based on using mixed Gamma-L valleys for electron transport are proposed to overcome the density of states (DOS) bottleneck. Improved current density over Si is demonstrated in GaAs/AlAsSb, GaSb/AlAsSb, and Ge-on-Insulator-based single gate thin-body n-channel transistors. Finally, a critical question that has to do with scaling is - How small a useful MOS transistor can be? As transistor channel lengths are scaled to lengths shorter than Lg \u3c 8 nm, direct source-drain tunneling starts to limit the transistor operation. Scaling approaches needed in this tunneling dominated regime are discussed using atomistic quantum mechanical simulations

Design Concepts of Terahertz Quantum Cascade lasers: Proposal for Terahertz Laser Efficiency Improvements

Conceptual disadvantages of typical resonant phonon terahertz quantum cascade lasers THz-QCLs are analyzed. Alternative designs and their combination within a concrete device proposal are discussed to improve the QCL performance. The improvements are 1 indirect pumping of the upper laser level, 2 diagonal optical transitions, 3 complete electron thermalization, and 4 materials with low effective electron masses. The nonequilibrium Green’s function method is applied to predict stationary electron transport and optical gain. The proposed THz-QCL shows a higher optical gain, a lower threshold current, and a higher operation temperature. Alloy disorder scattering can worsen the QCL performance

Performance Enhancement of GaAs UTB pFETs by Strain, Orientation and Body Thickness Engineering

II-V semiconductors can provide a viable option for continuous scaling of future CMOS technology [1-3]. We report a significant enhancement in the ON-current (ION) of ultra-thin body (UTB) GaAs intrinsic channel p-MOSFETs using biaxial compressive strain. Our theoretical investigation shows that valence bands (VB) become hyperbolic under compressive strain in GaAs rendering effective mass approximation (EMA) invalid. The ballistic ION(~Qinv (hole density) × Vinj (injection velocity)) is governed mainly by the asymptotic group velocity (Vgrp ~ α.Vinj) of the hyperbolic VBs, These bands can be engineered using GaAs body thickness (Tch) scaling, compressive strain value and wafer orientation. Vinj is primarily controlled by strain and Tch whereas, Qinv is governed mainly by the gate electrostatics, thus providing two separate design parameters to control ION. Isotropic strain enhances Vinj which gives a maximum improvement in ION of ~23-40% for [100]/(100) and [110]/(111) pMOSFETs for 5 nm body thickness at 4% compressive biaxial strain. Scaling body thickness from 5nm to 2nm improves ION by ~2X for all the device orientations considered in this study

Study of Ultra-Scaled SiGe/Si Core/Shell Nanowire FETs for CMOS Applications

SiGe/Si core/shell nanowire (NW) devices are promising candidates for the future generation MOSFETs providing better channel control and hole mobility [1-4]. These core-shell devices can be exploited both as p- and n-type devices [3]. The Si shell improves the semiconductor-oxide interface and enhances the device performances [1, 3]. The Germanium condensation technique [4] is able to provide high Ge content (\u3e50%) channel with Si as capping layer. In this work we investigate the viability of using these core/shell NWFETs for CMOS application

Performance Prediction of Ultrascaled SiGe/Si Core/Shell Electron and Hole Nanowire MOSFETs

The performances of ultrascaled SiGe nanowire field- effect transistors (NWFETs) are investigated using an atomistic tight-binding model and a virtual crystal approximation to de- scribe the Si and Ge atoms. It is first demonstrated that the band edges and the effective masses of both relaxed and strained SiGe bulk are accurately reproduced by our model. The band structure model is then coupled to a top-of-the-barrier quantum transport approach to simulate the output characteristics of ul- trascaled n/p SiGe NWFETs and explore their viability for future high-performance CMOS applications. We predict a considerable improvement of SiGe nFETs and pFETs over their Si counterparts for SiGe/Si core/shell structures