Crosstalk Delay Analysis in Very Deep Sub-Micron VLSI Circuits

This report presents the work conducted as part of my master's thesis. The topic chosen for this thesis is one of the current issues the VLSI (very large scale integration) design community is facing today: Signal Integrity. One of the major contributors of signal integrity problem is the crosstalk between the wires on an Integrated Circuit. This thesis reports the details of the Crosstalk problem, the existing solutions, and proposals for new solutions to tackle effectively the problem. The thesis has the following chapters

Quaternary Voltage-Mode Logic Cells and Fixed-Point Multiplication Circuits

Fixed-point multiplication architectures are designed and evaluated using a set of logic cells based on a radix-4, quaternary number system. The library of logic circuits is based on Field Effect Transistors (FETs) that have different voltage threshold levels. The resulting logic cell library is sufficient to implement all possible quaternary switching functions. The logic circuits operate in voltage mode where different ranges of voltages encode the logic levels. Voltage mode circuitry is used to minimize overall power dissipation characteristics. Analysis of the resulting multiplication circuits indicates that power dissipation characteristics are advantageous when compared to equivalent word-sized binary voltage mode configurations with no decrease in performance

Meeting the Sustainable Development Goals for Water and Sanitation

For CMOS feature size of 65 nm and below, local (or intra-die or within-die) variations in transistor Vt contribute stochastic variation in logic delay that is a large percentage of the nominal delay. Moreover, when circuits are operated at low voltage (Vdd ¿ 0.5 V), the standard deviation of gate delay becomes comparable to nominal delay, and the Probability Density Function (PDF) of the gate delay is highly non-Gaussian. This paper presents a computationally efficient algorithm for computing the PDF of logic Timing Path (TP) delay, which results from local variations. This approach is called Non-linear Operating Point Analysis for Local Variations (NLOPALV). The approach is implemented using commercial STA tools and integrated into the standard CAD flow using custom scripts. Timing paths from a 28 nm commercial DSP are analyzed using the proposed technique and the performance is observed to be within 5% accuracy compared to SPICE based Monte-Carlo analysis.Massachusetts Institute of Technology (Presidential Fellowship