Static power optimization of deep submicron CMOS circuits for dual V T

In this paper we address the problem of delay constrained minimiza-tion of leakage power of CMOS digital circuits for dualV T technol-ogy. A novel and efficient heuristic alogrithm based on circuit graph enumeration is proposed. The experimental results on the MCNC91 benchmark circuits show that up to an order of magnitude power re-duction can be achieved without any increase in delay.

Efficient Procedures for Minimizing the Standby Power in Dual V_T CMOS Circuits

In this paper we present efficient procedures for delay constrained minimization of the power due to leakage in CMOS digital circuits for a dual threshold voltage (V T ) technology. The availability of two or more threshold voltages on the same chip provides a new opportunity for circuit designers to make tradeoffs between power and delay. We present two efficient procedures that take as input a gate level netlist and assign the proper threshold voltage to each transistor so that the leakage power is minimized but without violating the delay constraints. Experimental results on the MCNC91 benchmark circuits show that up to one order of magnitude power reduction can be achieved without any delay increase when compared to a circuit where all transistors are low V T devices. 1 Introduction The advent of deep submicron devices has given rise to new challenges as well as new opportunities for the optimal design of CMOS circuits. Many of the parameters of a MOSFET that are traditionally co..

Macro-Instruction Generation for Dynamic Logic Caching

This paper outlines the synthesis of macroinstructions for dynamically reprogrammable FPGAs so that they may be easily generated, placed, and garbage collected at run-time. An overview of a dynamic logic caching computer that uses these macroinstructions is given and their use within this environment discussed. The synthesis of macro-instructions is illustrated with a basic example. Finally, the current state of development of a logic cache based computing platform and compiler/simulator workframe is presented. 1 Introduction Dynamically reconfigurable gate arrays can be used to implement time-sliced coprocessors. By changing the configuration in the gate array's static RAM during run time, the coprocessor changes function during the execution of the program to provide hardware support on an as-needed basis. Thinking of the co-processor as a hardware cache, operating in much the same way as a memory cache, can provide several important benefits for fast prototyping. The logic cache c..

Data Driven Power Optimization of Sequential Circuits

In this paper we present an efficient technique to reduce the power dissipation in a technology mapped CMOS sequential circuit based on logic and structural transformations. The power reduction is achieved by adding sequential redundancies from low switching activity gates to high switching activity gates (targets) such that the switching activities at the output of the targets are significantly reduced. We show that the power reducing transformations result in a circuit that is a valid replacement of the original. The notion of validity used here is that of a delay safe replacement [11, 12]. The potential transformations are found by direct logic implications applied to the circuit netlist. Therefore the complexity of the proposed transformation is polynomial in the size of the circuit, allowing the processing of large designs

Synthesis of Asynchronous Systems from Data Flow Specifications

This report presents a method for automatic synthesis of asynchronous digital systems from high-level data flow specifications. We present an extended data flow model that accurately reflects the behavior of the asynchronous components so that the data flow specification can be directly mapped into a hardware realization. In addition, we develop a timing model for the basic asynchronous building blocks and show how to derive the timing parameters of a composed system. This timing model can also be used at the data flow level, allowing designers to explore various design alternatives. We then describe a number of applications of the data flow specification for high-level synthesis such as schemes for resource sharing, local transformations for data flow description optimization, and allocation and sequencing of operations for given resources. Finally, we present two examples, a 16-bit multiplier and a 16-point FIR digital filter, where the number of modules have been altered at the data..

Data Driven Power Optimization of Sequential Circuits

In this paper we present an efficient technique to reduce the power dissipation in a technology mapped CMOS sequential circuit based on logic and structural transformations. The power reduction is achieved by adding sequential redundancies from low switching activity gates to high switching activity gates (targets) such that the switching activities at the output of the targets are significantly reduced. We show that the power reducing transformations result in a circuit that is a valid replacement of the original. The notion of validity used here is that of a delay safe replacement [11, 12]. The potential transformations are found by direct logic implications applied to the circuit netlist. Therefore the complexity of the proposed transformation is polynomial in the size of the circuit, allowing the processing of large designs. 1 Introduction Reduction of power consumption in digital circuits has become an increasingly important design optimization goal. At the stage of logic optim..