Synthesis of Asynchronous Systems from Data Flow Specifications

Abstract

This report presents a method for automatic synthesis of asynchronous digital systems from high-level data flow specifications. We present an extended data flow model that accurately reflects the behavior of the asynchronous components so that the data flow specification can be directly mapped into a hardware realization. In addition, we develop a timing model for the basic asynchronous building blocks and show how to derive the timing parameters of a composed system. This timing model can also be used at the data flow level, allowing designers to explore various design alternatives. We then describe a number of applications of the data flow specification for high-level synthesis such as schemes for resource sharing, local transformations for data flow description optimization, and allocation and sequencing of operations for given resources. Finally, we present two examples, a 16-bit multiplier and a 16-point FIR digital filter, where the number of modules have been altered at the data..