Integrated circuit having clock-line control and method for testing same

An integrated circuit includes a plurality of interconnected circuit modules having memory elements and logic elements therein. The modules collectively perform the operations of the integrated circuit. However, rather than testing the entire circuit and limiting the degree of fault coverage, individual modules can be tested on a module by module basis. To facilitate testing at the module level, the circuit includes a plurality of control cells connected to respective ones of the modules. Each of the control cells preferably includes a shift register latch for retaining a data signal corresponding to whether the respective module is to be sequentially tested or temporarily disabled. The control cells further comprise a pass-through transistor network for passing the system clock to one or more of the modules under test and for withholding the clock from the modules not under test. The method of the present invention includes steps for disabling one or more modules which are not under test and enabling those modules which are to be tested. The enabled modules are then tested sequentially, preferably using one or more outputs from the disabled modules. Testing of the integrated circuit occurs on a module by module basis until all modules are tested.Board of Regents, University of Texas Syste

DDR4 Data Channel Failure Due to DC Offset Caused by Intermittent Solder Ball Fracture in FBGA Package

This paper shows that an intermittent AC coupling defect occurring in a DDR4 data channel will cause more intermittent errors in DDR4, compared to such defect in DDR3. The intermittent AC coupling defect occurs due to intermittent fracture in DDR4 package solder ball. The defect causes DC offset in DDR4, which shifts the data signal or data eye and results in DDR4 data channel failure. The DC offset occurs due to the asymmetric nature of pseudo open drain termination scheme. DDR4 data channel response is compared with DDR3 channel. It is shown that pseudo random binary sequence (PRBS) pattern will always cause failure for DDR4, but PRBS will only cause failure in DDR3 if the sequence of consecutive 0's or 1's in PRBS pattern is long enough to cause threshold violation. As a result there will be more intermittent errors in DDR4 compared to DDR3. The defect due to fracture in solder ball is modelled by an AC coupling capacitor. A 1nF AC coupling capacitor corresponding to a solder ball fracture of height about 1nm is used to show the difference between DDR4 and DDR3 response

Temperature Estimation of HBM2 Channels with Tail Distribution of Retention Errors in FPGA-HBM2 Platform

High-bandwidth memory 2 (HBM2) vertically stacks multiple dynamic random-access memory (DRAM) dies to achieve a small form factor and high capacity. However, it is difficult to diagnose HBM2 issues owing to their structural complexity and 2.5D integration with heterogeneous chips. The effects of the temperature at the base logic die (TL), and the refresh interval at the stacked DRAM dies, were experimentally investigated by counting the dynamic retention errors in the eight channels in an HBM2. TL was indirectly controlled by the heatsink temperature (TS). The lognormal distribution represents the distribution of the cell counts with varying refresh times. All Z-magnitudes (multiples of the distribution standard deviation) over the various refresh cycle times (RCTs) up to 2.045 s in a single channel at TL of 70 °C appeared below 4.4, which means that the error bits belong to the tail distribution. The Z-differences in the eight channels were distinctively larger than the Z-differences of the same channels at a constant temperature, demonstrating that the temperature difference in the stacked dies resulted in larger Z-differences. The largest Z-difference was 0.091 for all the channels at an RCT of 1.406 s, which was approximately 4.82 times smaller than the Z-difference between the TL temperatures of 70 °C and 80 °C in a single channel. The Z-difference between the TL temperatures of 70 °C and 72 °C in a single channel was approximately the same as the Z-difference in all the channels at an RCT of 2.045 s