Multi-criteria Resource Allocation in Modal Hard Real-Time Systems

In this paper, a novel resource allocation approach dedicated to hard real-time systems with distinctive operational modes is proposed. The aim of this approach is to reduce the energy dissipation of the computing cores by either powering them off or switching them into energy-saving states while still guaranteeing to meet all timing constraints. The approach is illustrated with two industrial applications, an engine control management and an engine control unit. Moreover, the amount of data to be migrated during the mode change is minimised. Since the number of processing cores and their energy dissipation are often negatively correlated with the amount of data to be migrated during the mode change, there is some trade-off between these values, which is also analysed in this paper

Very large-scale neuromorphic systems for biological signal processing

This chapter is a white paper describing a platform for scaled-up neuromorphic systems to ‘human brain size’ complexity. Such a system will be necessary for massive search and analysis tasks while interacting with biological data. This system would consist of similar number of neurons and synapses as in an adult human brain. One of the largest bottlenecks is the huge synaptic complexity that would result from connecting billions of neurons. The purpose of this chapter is to describe a feasible architecture that could handle the enormous communication bandwidth necessary for such a large-scale neuromorphic system. The proposed approach is grounded in the assumption that we would only be able to appreciate the utility of a neuromorphic system when it is somewhat similar to the human brain in terms of energy consumption and size. Inspired by the recent advancements in SoC architecture, a novel scalable intercluster communication network is proposed here. A particularly useful instantiation of this occurs for the global synaptic communication, interconnecting the local clusters of synapse arrays. The core of the proposed solution is a novel switching architecture in the CMOS back end of line (BEOL) that is expected to be extremely power efficient. In contrast to a fixed predefined bus that is shared over all connected local clusters, the proposed solution will allow a multitude of dedicated point-to-point connections that can be switched dynamically