All photonic analogue to digital and digital to analogue conversion techniques for digital radio over fibre system applications

Copyright @ 2011 IEEEWideband electronic analogue to digital conversion (ADC) systems have critical problems encountered in high-frequency broadband communication systems that the recent electronic ADCs (EADC) have experienced those such as uncertainty of sampling time. In this paper, an all photonic sampling and quantization ADC and photonic digital to analogue conversion system with six effective number of bits (ENOB) is designed. By using this photonic ADC (PADC), a novel digital radio over fibre link for wireless radio frequency (RF) signal transportation over 20 Km single mode fibre has been designed whose performance is investigated in this paper. In the digital radio over fibre, the dynamic range is independent of the fibre length

Digital radio over fibre for future broadband wireless access network solution

Copyright @ 2010 IEEEDigital systems are more flexible and environment-process-tolerant than analogue systems. They are more reliable and robust against cross-talk, interference and channel noises, and are capable of covering higher dynamic range than analogue systems. Wideband electronic analogue to digital conversion (ADC) systems have critical problems encountered in high-frequency broadband communication systems that the recent electronic ADCs (EADC) have experienced those such as uncertainty of sampling time. In this paper, an 80Gigasample/s all photonic sampling and quantization ADC and photonic digital to analogue conversion system with six effective number of bits (ENOB) is designed. By using this Photonic ADC (PADC), a digital radio over fibre link for wireless radio frequency (RF) signal transportation over 50 km single mode fibre has been designed whose performance is investigated in this paper

Tertiary-Tree 12-GHz 32-bit Adder in 65nm Technology

This paper presents a new 32-bit adder structure with 12 GHz low-power operation in 65nm technology. The Fast Conditional Sparse-Tree Logic (FCSL) is based on modifying the initial Sparse-Tree architecture [1] to enhance its speed using tertiary trees and applying a carry-select scheme in some of the more significant bits. This design has been compared with the Sparse-Tree adder and the Low-Voltage Swing adder in terms of speed and power. It has been shown that speed can be improved using FCSL architecture while keeping the power at a comparable level

A LOW-POWER FULLY INTEGRATED GAUSSIAN-MSK MODULATOR BASED ON THE SIGMA-DELTA FRACTIONAL-N FREQUENCY SYNTHESIS

ABSTRACT A fully integrated GMSK modulator in DRRS band is presented. All components of the transmitter except the power amplifier, including the loop filter and the oscillator are on-chip. Transistor and system level simulations demonstrate that the modulator meets the performance requirements of the DRRS standard. The circuit power consumption of the modulator at 1.4GHz is 37mW with a single 3V power supply, in a 0.6µm digital CMOS technology. Low power consumption of the modulator is due to the low-power frequency divider and low-power low-phase noise ring oscillator

A Genetic-Algorithm Solution for Designing Optimal Forwarding Tables

Abstract. A high speed IP address lookup engine with a reasonable memory cost is a key factor for designing a router at wire speed. This paper proposes a hardware solution that performs each IP address lookup in a few number of memory accesses with minimum amount of memory requirement. Our solution is based on dividing destination IP address into several segments. For finding the optimum address segmentation that minimizes the memory consumption, a genetic-algorithm solution is employed. The genetic program uses benchmark forwarding tables for finding the optimum points of address segmentation. The final result is a small forwarding table for the local traffic of the router. This table can be reconfigured along the time when the local traffic gradually changes. The proposed method can fit a forwarding table of size 130000 routing prefixes in about 1.5 MB of memory with only four memory accesses for each lookup search.