Roughness improvement of the CoSi2/Si interface for an application as buried silicide

The material COSi2 is preferred for the fabrication of buried silicide films between silicon device layer and buried oxide of SOI substrates for BICMOS integrations. Such an application needs excellent quality of the interface between the silicide and the silicon device layer. Using the conventional cobalt salicide process the roughness and waviness of the interface is too large for a device application. In this presentation three technologies to improve the COSi2/Si-interface quality were characterized. Using the first technology a very thin single crystalline COSi2 film was fabricated on a silicon substrate. This film acts as initial layer to produce thicker single crystalline silicide films. By the second technology an interlayer between cobalt and the silicon substrate was used to mediate an epitaxial COSi2 growth. Different types and materials were tested. Using the third technique a sacrificial layer of polycrystalline silicon between cobalt and the silicon substrate was consumed during the silicidation reaction. This method gives the best results with interface roughness values of less than 1 nm. The interface roughness was measured after COSi2 removal using AFM. A possible epitaxial growth of the silicide films was investigated with XRD analysis. Cross sectional SEM images were prepared to analyze the interface waviness and the COSi2 structure. (C) 2007 Published by Elsevier B.V

Different approaches to integrate patterned buried CoSi2 layers in SOI substrates

The fabrication of a new silicon on silicide on insulator (SSOI) substrate for the integration of bipolar and CMOS devices on the same wafer is demonstrated. This structure includes a 500 nm thick buried oxide (BOX) and a 90 nm patterned cobalt disilicide film under a 300 nm thick silicon device layer. Two different process flows were used to build the final SSOI substrate. The first process bases on the known BESOI regime and includes wafer grinding and polishing steps. The second technology is a modified variant of the SmartCut (TM) method, where the SOI substrates are formed using hydrogen implantation, wafer splitting and CMP polishing. The cobalt disilicide was produced using a conventional cobalt salicide process. This process consists of cobalt deposition, two RTA steps and a selective etch. Some modifications in the salicide regime were made to improve the interface between the CoSi2 and the device silicon. (c) 2006 Published by Elsevier B.V