VHDL-based Modelling Approach for the Digital Simulation of 4-phase Adiabatic Logic Design

In comparison to conventional CMOS (non-adiabatic logic), the verification of the functionality and the low energy traits of adiabatic logic techniques are generally performed using transient simulations at the transistor level. However, as the size and complexity of the adiabatic system increases, the amount of time required to design and simulate also increases. Moreover, due to the complexity of synchronizing the power-clock phases, debugging of errors becomes difficult too thus, increasing the overall verification time. This paper proposes a VHSIC Hardware Descriptive Language (VHDL) based modelling approach for developing models representing the 4-phase adiabatic logic designs. Using the proposed approach, the functional errors can be detected and corrected at an early design stage so that when designing adiabatic circuits at the transistor level, the circuit performs correctly and the time for debugging the errors can substantially be reduced. The function defining the four periods of the trapezoidal AC power-clock is defined in a package which is followed by designing a library containing the behavioral VHDL models of adiabatic logic gates namely; AND/NAND, OR/NOR and XOR/XNOR. Finally, the model library is used to develop and verify the structural VHDL representation of the 4-phase 2-bit ring-counter and 3-bit up-down counter, as a design example that demonstrates the practicality of the proposed approach

Adiabatic Flip-Flops and Sequential Circuit Design using Novel Resettable Adiabatic Buffers

We propose novel resettable adiabatic buffers for five adiabatic logic families namely; Efficient Adiabatic Charge Recovery Logic (EACRL), Improved Efficient Charge Recovery Logic (IECRL), Positive Feedback Adiabatic Logic (PFAL), Complementary Pass-transistor Adiabatic Logic (CPAL) and Clocked Adiabatic Logic (CAL). We present the design of resettable flip-flops using the proposed buffers. The proposed flip-flops alleviate the problem of increased energy and area consumption incurred by the existing mux-based resettable flip-flops. We then design the 3-bit up-down counters and extended our comparison beyond energy dissipation using the above five adiabatic logic families. PFAL based sequential circuit designs gives the best performance trade-offs in terms of complexity, energy, speed and area compared to the other adiabatic designs

Automated Malaria Parasite Detection in Thin Blood Films:- A Hybrid, Illumination and Colour Constancy Insensitive Morphological Approach

This paper illustrates the automated diagnosis of malaria parasite (Plasmodium species) in microscopic images of Giemsa stained thin blood films. The procedure adapts a morphological approach for blood cell identification and uses the image features such as intensity, histogram, relative size and geometry for further analysis. Two methods of object classification have been described for parasite detection; one based on relative size and morphology and the other based on intensity variation. An analytical study on both methods has been performed further to validate the accuracy of the methods

Hardware implementation of Modified Annular Ring Ratio for Blood Cell Detection in Thin Blood Smear Images

Malaria continues to spread in endemic areas. This deadly disease is the subject of multiple researches in terms of patient diagnoses. Post treatment diagnoses are necessary to make sure that patients treated for malaria continue to be free from Plasmodium protozoan parasites. Fast and automated analyses are possible with image processing of blood cell samples. This paper proposes a modified version of an image processing algorithm named Annular Ring Ratio, which identifies and locates the blood cell present in the thin blood smear images, to make the algorithm amenable to efficient hardware implementation through the elimination of the costly division process. The Annular Ring Ratio process identifies circular shapes through the calculation of a ratio between two circular areas. With proper configuration it can detect cell and parasite positions leading to the identification of infected cells and further estimate the level of infections

Using the enneagram for market segmentation

Session 6.4 New Products IISegmentation and positioning constitute the crux of marketing strategy. Over the past two decades, lifestyle and psychographics have been increasingly used as a basis for market segmentation. This paper illustrates how the ancient and mystical technique of the Enneagram can be effectively used as a base for psychographic segmentation. With the Enneagram finding ever-increasing applications in strategic management and human resource development, it is only fitting that scholars in marketing harness the diagnostic and predictive power of the Enneagram. However, adoption of the Enneagram for marketing purposes will require further conceptual development and empirical analysis.Rajeev Kamineni and Sudhir Kal

Design and low-power implementation of an adaptive image rejection receiver

This paper deals with and details the design and implementation of a low-power; hardware-efficient adaptive self-calibrating image rejection receiver based on blind-source-separation that alleviates the RF analog front-end impairments. Hybrid strength-reduced and re-scheduled data-flow, low-power implementation of the adaptive self-calibration algorithm is developed and its efficiency is demonstrated through simulation case studies. A behavioral and structural model is developed in Matlab as well as a low-level architectural design in VHDL providing valuable test benches for the performance measures undertaken on the detailed algorithms and structures

Multi-Stage Complex Notch Filtering for Interference Detection and Mitigation to Improve the Acquisition Performance of GPS

Continuous Wave Interferences (CWIs) can degrade the accuracy of a Global Positioning System (GPS) receiver and moreover it can completely deteriorate receiver’s normal operation. In this paper a low-cost anti-jamming system design is presented for the mitigation and detection of CWIs for GPS receivers. The anti-jamming system comprises of parameterizable Complex Adaptive Notch Filter (CANF) module which is able to detect and excise single or multiple CWIs. The CANF module is composed of a first, second and third order infinite-impulse response filter with an Auto-Regressive Moving Averager structure. The proposed CANF detects the existence of the CWI and estimates JNR level of incoming signal by using the statistical value of the adaptive parameter b0. The impact of the CANF module on the acquisition is analyzed. Moreover, a simple and innovative system level model is proposed which can utilize each CANF efficiently with threshold setting of JNR estimation within the adaptation block. Threshold setting parameters provide trade-off between effective excision of CWI, order of the filter and power consumption. This results in a parameterizable CANF module and provide effective solution for the mitigation of interferences with a high-power profile for GPS based applications