A Review on Performances of Reversible Ripple-Carry Adders

Quantum computing and circuits are of growing interest and so is reversible logic as it plays an important role in the synthesis of quantum circuits. Moreover, reversible logic provides an alternative to classical computing machines, that may overcome many of the power dissipation problems in the near future. Some ripple-carry adders based on a do-spy-undo structure have been designed and tested reversibly. This paper presents a brief overview of the performances obtained with such chips processed in standard 0.35 um CMOS technology and used in true reversible calculation (computations are performed forwards and backwards such that addition and subtraction are made reversibly with the same chip). Adiabatic signals used are known to allow the signal energy stored on the various capacitances of the circuit to be redistributed rather than being dissipated as heat while allowing to avoid calculation errors introduced by the use of conventional rectangular pulses. Through the example of both simulations and experimental results, this paper aims at providing a base of knowledge and knowhow in physical implementation of reversible circuits

A Review on Performances of Reversible Ripple-Carry Adders

Quantum computing and circuits are of growing interest and so is reversible logic as it plays an important role in the synthesis of quantum circuits. Moreover, reversible logic provides an alternative to classical computing machines, that may overcome many of the power dissipation problems in the near future. Some ripple-carry adders based on a do-spy-undo structure have been designed and tested reversibly. This paper presents a brief overview of the performances obtained with such chips processed in standard 0.35 um CMOS technology and used in true reversible calculation (computations are performed forwards and backwards such that addition and subtraction are made reversibly with the same chip). Adiabatic signals used are known to allow the signal energy stored on the various capacitances of the circuit to be redistributed rather than being dissipated as heat while allowing to avoid calculation errors introduced by the use of conventional rectangular pulses. Through the example of both simulations and experimental results, this paper aims at providing a base of knowledge and knowhow in physical implementation of reversible circuits

Underlap Channel UTBB MOSFETs for Low-Power Analog/RF Applications

In this work, we report on the significance of underlap channel architecture in Ultra Thin Body BOX (UTBB) fully-depleted (FD) SOI MOSFETs to improve analog/RF performance metrics. It is shown that at lower current levels and shorter gate lengths, underlap UTBB MOSFETs can achieve significant improvement > 1.5 times in key analog/RF metrics over devices designed with conventional S/D architecture. Analog/RF figures of merit are analyzed in terms of spacer-to-straggle ratio (s/sigma), a key parameter for the design of underlap devices. Results suggest that underlap S/D design with s/sigma ratio of 3.3 is optimum to enhance analog/RF metrics at low current levels (< 60 muA/mum). The present work provides new viewpoints for realizing future low-power analog devices/circuits with underlap UTBB FETs

Analog/RF Performance of sub-100 nm SOI MOSFETs with Non-Classical Gate-Source/Drain Underlap Channel Design

In this work, we analyze the potential of non-overlap (also known as underlap) source/drain (S/D) channel architecture to improve analog/RF performance metrics of sub-100 nm Ultra Thin Body BOX (UTBB) SOI MOSFETs. It is shown that underlap S/D design results in higher voltage gain (AVO) and cut-off frequency (fT) along with a broader analog `sweet spot' in nanoscale MOSFETs thus offering new possibilities for analog/RF scaling below 60 nm. The advantages offered by underlap channel design are not limited to lower current levels (~10 ¿A/¿m) but extend up to 100 ¿A/¿m which corresponds to optimum AVO and fT performance for most circuit applications. For shorter gate length devices, underlap design results in an impressive 20% improvement in fT along with a 2 fold enhancement in AVO. This work provides new opportunities for realizing future low-power analog/RF design with underlap UTBB MOSFETs

Retention in metal-oxide-semiconductor structures with two embedded self-aligned Ge-nanocrystal layers

Structural and electrical characterization has been carried out on metal–oxide–semiconductor (MOS) structures with a silicon dioxide (SiO2) layer containing a germanium nanocrystals (Ge-ncs) floating gate. Ge-nc layers were embedded in SiO2 by ion implantation with subsequent annealing. Structural analysis proved the presence of two self-aligned nanocrystal layers within the SiO2 host material. The electrical results indicate a strong memory effect due to the presence of a near-interface Ge-nc layer. Few volts memory windows can easily be obtained at relatively low programming voltages (<6 V). For comparison, operating voltages used in current FLASH technology are about 12 V. Despite its promising structural properties, retention times extracted from capacitance measurements and scanning Kelvin microscopy were found to be too low (~105 s) to comply with the non-volatility industry requirements (<10 years required)

Structural properties of Ge-implanted SiO2 layers and related MOS memory effects

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Underlap channel UTBB MOSFETs for low-power analog/RF applications

In this work, we report on the significance of underlap channel architecture in Ultra Thin Body BOX (UTBB) fully-depleted (FD) SOI MOSFETs to improve analog/RF performance metrics. It is shown that at lower current levels and shorter gate lengths, underlap UTBB MOSFETs can achieve significant improvement > 1.5 times in key analog/RF metrics over devices designed with conventional S/D architecture. Analog/RF figures of merit are analyzed in terms of spacer-to-straggle ratio (s/ sigma ), a key parameter for the design of underlap devices. Results suggest that underlap S/D design with s/ sigma ratio of 3.3 is optimum to enhance analog/RF metrics at low current levels (< 60 mu A/ mu m). The present work provides new viewpoints for realizing future low-power analog devices/circuits with underlap UTBB FETs.Anglai