Characterization of superconducting through-silicon vias as capacitive elements in quantum circuits

The large physical size of superconducting qubits and their associated on-chip control structures presents a practical challenge towards building a large-scale quantum computer. In particular, transmons require a high-quality-factor shunting capacitance that is typically achieved by using a large coplanar capacitor. Other components, such as superconducting microwave resonators used for qubit state readout, are typically constructed from coplanar waveguides which are millimeters in length. Here we use compact superconducting through-silicon vias to realize lumped element capacitors in both qubits and readout resonators to significantly reduce the on-chip footprint of both of these circuit elements. We measure two types of devices to show that TSVs are of sufficient quality to be used as capacitive circuit elements and provide a significant reductions in size over existing approaches

Radiation effects in MIT Lincoln Lab 3DIC technology

We characterized TID effects in MITLL 3DIC technology. We found that the effects were comparable for nFETs on the bottom tier with that on single tier wafers. Less positive charge build-up is observed for wide nFETs on the upper tiers, and this is due to the absence of silicon below the BOX. Other results indicate that MITLL 3DIC technology can be hardened to ionizing radiation by modifying the BOX.United States. Defense Threat Reduction Agency (Air Force Contract FA8721-05-C-0002)United States. Defense Advanced Research Projects Agenc

Channel engineering of SOI MOSFETs for RF applications

Channel engineering of SOI MOSFETs is explored by altering ion implantation without adding any new fabrication steps to the standard CMOS process. The effects of implantation on characteristics important for RF applications, such as transconductance, output resistance, breakdown voltage, are compared. Data show that the best overall RF MOSFET has no body and drain-extension implants.Defense Advanced Research Projects Agency (Air Force Contract FA8721-05-C-0002

• FRITZE ET AL. Subwavelength Optical Lithography with Phase-Shift Photomasks Subwavelength Optical Lithography with

■ Optical lithography has been the patterning method of choice for the semiconductor industry for over three decades. Through a continual decrease in exposure wavelength and increase in lens numerical aperture, this technology has kept pace with the exponentially shrinking feature sizes predicted by Moore’s law. In the mid-1990s, minimum feature sizes on semiconductor chips began to drop below the available imaging wavelengths, ushering in the era of subwavelength optical lithography. Imaging in this challenging regime has been enabled by the development of resolution enhancement technologies (RETs) that work to overcome diffraction limits on imaging resolution. We have developed, as part of a Defense Advanced Research Projects Agency–sponsored program in advanced complementary metal-oxide semiconductor (CMOS) technology, phase-shift-photomask optical lithography processes capable of imaging features as small as 16 % of the exposure wavelength. We have applied these processes to the development of advanced silicon-on-insulator (SOI) device technology utilizing standard commercial optical lithography equipment

Silicon Hard-Stop Spacers for 3D Integration of Superconducting Qubits

© 2019 IEEE. As designs for superconducting qubits become more complex, 3D integration of two or more vertically bonded chips will become necessary to enable increased density and connectivity. Precise control of the spacing between these chips is required for accurate prediction of circuit performance. In this paper, we demonstrate an improvement in the planarity of bonded superconducting qubit chips while retaining device performance by utilizing hard-stop silicon spacer posts. These silicon spacers are defined by etching several microns into a silicon substrate and are compatible with 3D-integrated qubit fabrication. This includes fabrication of Josephson junctions, superconducting air-bridge crossovers, underbump metallization and indium bumps. To qualify the integrated process, we demonstrate high-quality factor resonators on the etched surface and measure qubit coherence (T1, T2,echo > 40 μs) in the presence of silicon posts as near as 350 μm to the qubit

Wafer-scale 3D integration of silicon-on-insulator RF amplifiers

RF amplifiers are demonstrated using a three- dimensional (3D) wafer-scale integration technology based on silicon-on-insulator (SOI) CMOS process. This new 3D implementation reduces the amplifier size and shortens interconnects for smaller loss and delay. In addition, 3D integration allows the stacking of wafers fabricated using different process technologies to optimize the overall circuit performance at the lowest cost. In RF amplifier examples, MOSFETs and passive components are placed on separate tiers to reduce the size. Measured amplifier performance agrees well with simulation and footprint reduction of approximately 40% comparing to conventional 2D layout can be achieved.United States. Defense Advanced Research Projects Agency (Air Force Contract FA8721-05-C-0002

Wafer-scale 3D integration of InGaAs image sensors with Si readout circuits

In this work, we modified our wafer-scale 3D integration technique, originally developed for Si, to hybridize InP-based image sensor arrays with Si readout circuits. InGaAs image arrays based on the InGaAs layer grown on InP substrates were fabricated in the same processing line as silicon-on-insulator (SOI) readout circuits. The finished 150-mm-diameter InP wafer was then directly bonded to the SOI wafer and interconnected to the Si readout circuits by 3D vias. A 1024 times 1024 diode array with 8-mum pixel size is demonstrated. This work shows the wafer-scale 3D integration of a compound semiconductor with Si.Defence Advanced Research Projects Agency (Air Force Contract FA8721-05-C-0002

Behavioral Deficits at 18-22 Months of Age Are Associated with Early Cerebellar Injury and Cognitive and Language Performance in Children Born Extremely Preterm

To investigate associations in toddlers born extremely preterm (<28 weeks) between neonatal neuroimaging and 18- to 22-month developmental and behavioral outcomes. Cohort analysis from the Eunice Kennedy Shriver National Institute of Child Health and Human Development Neonatal Research Network Surfactant Positive Airway Pressure and Pulse Oximetry Trial Neuroimaging and Neurodevelopmental Outcomes Study of infants born extremely preterm. Subjects underwent cranial ultrasonography and near-term magnetic resonance imaging (MRI). At 18-22 months of corrected age, the assessment included the Brief Infant Toddler Social Emotional Assessment (BITSEA) Problem and Competence Scale scores and the Bayley Scales of Infant Development, Third Edition (Bayley-III). The BITSEA Problem Scale assesses dysregulation; the Competence Scale assesses social-emotional competence. We examined associations of Problem and Competence scores and positive screen rates with cranial ultrasonography and near-term MRI. Mean BITSEA and Bayley-III scores were compared using ANOVA and positive screen rates with the χ2 test. We computed correlations between BITSEA and Bayley-III scores. Of the 397 children, positive BITSEA screens were found in 34% for the Problem score and 26% for the Competence score. Presence of lesions on near-term MRI that included cerebellar lesions were significantly associated with lower BITSEA Competence but not with Problem scores; Competence scores were inversely related to the presence/significance of lesions. Positive screens on Competence scores and on both Competence and Problem scores were significantly associated with Bayley-III cognitive and language scores <85 (P < .001). Social–emotional competence contributes to deficits in cognitive and language development. Presence of injury on near-term MRI that includes cerebellar lesions is associated with later social–emotional competence and may be a useful predictor to guide early assessment and intervention. ClinicalTrials.gov: NCT00063063 and NCT00233324