Scalable trajectory methods for on-demand analog macromodel extraction.

ABSTRACT Trajectory methods sample the state trajectory of a circuit as it simulates in the time domain, and build macromodels by reducing and interpolating among the linearizations created at a suitably spaced subset of the time points visited during training simulations. Unfortunately, moving from simple to industrial circuits requires more extensive training, which creates models too large to interpolate efficiently. To make trajectory methods practical, we describe a scalable interpolation architecture, and the first implementation of a complete trajectory "infrastructure" inside a full SPICE engine. The approach supports arbitrarily large training runs, automatically prunes redundant trajectory samples, supports limited hierarchy, enables incremental macromodel updates, and gives 3-10X speedups for larger circuits

Spatial variation decomposition via sparse regression

In this paper, we briefly discuss the recent development of a novel sparse regression technique that aims to accurately decompose process variation into two different components: (1) spatially correlated variation, and (2) uncorrelated random variation. Such variation decomposition is important to identify systematic variation patterns at wafer and/or chip level for process modeling, control and diagnosis. We demonstrate that the spatially correlated variation can be accurately represented by the linear combination of a small number of “templates”. Based upon this observation, an efficient algorithm is developed to accurately separate spatially correlated variation from uncorrelated random variation. Several examples based on silicon measurement data demonstrate that the aforementioned sparse regression technique can capture systematic variation patterns with high accuracy.Interconnect Focus Center (United States. Defense Advanced Research Projects Agency and Semiconductor Research Corporation)Focus Center Research Program. Focus Center for Circuit & System SolutionsNational Science Foundation (U.S.) (Contract CCF-0915912

A class of cellular computer architectures to support physical design automation

http://deepblue.lib.umich.edu/bitstream/2027.42/7379/5/bad1753.0001.001.pdfhttp://deepblue.lib.umich.edu/bitstream/2027.42/7379/4/bad1753.0001.001.tx

Beyond low-order statistical response surfaces: latent variable regression for efficient, highly nonlinear fitting

The number and magnitude of process variation sources are increasing as we scale further into the nano regime. Today’s most successful response surface methods limit us to low-order forms-- linear, quadratic-- to make the fitting tractable. Unfortunately, not all variational scenarios are well modeled with low-order surfaces. We show how to exploit latent variable regression ideas to support efficient extraction of arbitrarily nonlinear statistical response surfaces. An implementation of these ideas called SiLVR, applied to a range of analog and digital circuits, in technologies from 90 to 45nm, shows significant improvements in prediction, with errors reduced by up to 21X, with very reasonable runtime costs

FPGA routing and routability estimation via Boolean satisfiability

Abstract—Guaranteeing or even estimating the routability of a portion of a placed field programmable gate array (FPGA) remains difficult or impossible in most practical applications. In this paper, we develop a novel formulation of both routing and routability estimation that relies on a rendering of the routing constraints as a single large Boolean equation. Any satisfying assignment to this equation specifies a complete detailed routing. By representing the equation as a binary decision diagram (BDD), we represent all possible routes for all nets simultaneously. Routability estimation is transformed to Boolean satisfiability, which is trivial for BDD’s. We use the technique in the context of a perfect routability estimator for a global router. Experimental results from a standard FPGA benchmark suite suggest the technique is feasible for realistic circuits, but refinements are needed for very large designs. Index Terms — Computer-aided design, field programmable gate array (FPGA), placement, rapid prototype, routing. I

Performance-Driven Simultaneous Placement and Routing for FPGA’s

Sequential place and route tools for FPGAs are inherently weak at addressing both wirability and timing optimizations. This is primarily due to the difficulty of accurately predicting wirability and delay during placement. A new performance-driven simultaneous placement / routing technique has been developed for island-style FPGA designs. On a set of industrial designs for Xilinx 4000-series FPGAs, our scheme produces 100 % routed designs with 8%-15 % improvement in delay when compared to the Xilinx XACT5.0 place and route system.