On How Network Architecture Determines the Dominant Patterns of Spontaneous Neural Activity

In the absence of sensory stimulation, neocortical circuits display complex patterns of neural activity. These patterns are thought to reflect relevant properties of the network, including anatomical features like its modularity. It is also assumed that the synaptic connections of the network constrain the repertoire of emergent, spontaneous patterns. Although the link between network architecture and network activity has been extensively investigated in the last few years from different perspectives, our understanding of the relationship between the network connectivity and the structure of its spontaneous activity is still incomplete. Using a general mathematical model of neural dynamics we have studied the link between spontaneous activity and the underlying network architecture. In particular, here we show mathematically how the synaptic connections between neurons determine the repertoire of spatial patterns displayed in the spontaneous activity. To test our theoretical result, we have also used the model to simulate spontaneous activity of a neural network, whose architecture is inspired by the patchy organization of horizontal connections between cortical columns in the neocortex of primates and other mammals. The dominant spatial patterns of the spontaneous activity, calculated as its principal components, coincide remarkably well with those patterns predicted from the network connectivity using our theory. The equivalence between the concept of dominant pattern and the concept of attractor of the network dynamics is also demonstrated. This in turn suggests new ways of investigating encoding and storage capabilities of neural networks

iButton Enrolment and Verification Requirements for the Pressure Sequence Smartcard Biometric

With the growing number of smartcard applications there comes an increasing need to restrict access to the card itself. In previous work we proposed the pressure sequence biometric, within which a biometric sensor is integrated onto the card in a low-cost and mechanically compliant manner. Using an off-card verifier we demonstrated reasonable discrimination between users. In this paper we consider a number of on-card verification schemes, the best of which offers an equal error rate of 2.3%. On-card computational time requirements were found to be 3.1 seconds for enrolment and 0.12 seconds for verification. Incorporating our implementation into an existing applet used 684 bytes of program space. Whilst data memory requirements are estimated to be 1400 and 300 bytes for enrolment and verification, respectively. These time and size requirements demonstrate our biometric as a practical proposition for the protection of smart cards. Experiments were performed with the iButton's Java Card platform