40 research outputs found

    Delay partitioning helps reducing variability in 3DVLSI

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    International audience3DVLSI is an emerging more than Moore technology. In this paper, we propose 3D design methodologies dealing with process variability. Using SPICE models and Monte Carlo simulations we show a delay partioning method for stacked circuits to reduce frequency dispersion by 30%. We also compare how the process correlation between tiers influences the design corners

    Explicit compact model of independent double-gate MOSFET

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    International audienc

    Wideband characterization of body-accessed PD SOI MOSFETs with multiport measurements

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    In this work we present an original method based on 3-port RF measurements to accurately extract the body resistance (R/sub be/) in body-accessed PD SOI MOSFETs. This method can be used to assess the validity of compact models such as BSIMSOI. The RF body access also enabled a precise characterization of intrinsic and extrinsic body capacitances. A complete 3-port model was then derived and further validated on DT MOSFET measurements by connecting the body to the gate terminal.Anglai
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