Tunable Lossy and Lossless Grounded Inductors Using Minimum Active and Passive Components

In this contribution, nine new Grounded Inductance Simulators (GISs) using a single Multiple-Output Current Controlled Current Conveyor Transconductance Amplifier (MO-CCCCTA) and one grounded capacitor are proposed. Among them, two are lossless types and seven are lossy types. The use of a single grounded capacitor makes the circuits suitable for fabrication. All the proposed circuits are electronically tunable through the bias currents of MO-CCCCTA. Furthermore, no component matching conditions are needed for realizing them. The designed circuits are verified through PSPICE simulator with ± 0.9 V power supply. The simulation results show that for all the proposed circuits: maximum operating frequencies are about 12 MHz, power dissipation is less than 0.784 mW, Total Harmonic Distortions (THDs) are under 8.09%, and maximum output voltage noise at 1 MHz frequency is 14.094 nV/√Hz. To exhibit the workability of the proposed circuits, they are used to design band-pass, low-pass filter, parallel RLC resonator, and parasitic inductance cancelator

Voltage Differencing Current Conveyor Based Voltage-Mode and Current-Mode Universal Biquad Filters with Electronic Tuning Facility

The objective of this study is to present four new universal biquad filters, two voltage-mode multi-input-single-output (MISO), and two current-mode single-input-multi-output (SIMO). The filters employ one voltage differencing current conveyor (VDCC) as an active element and two capacitors along with two resistors as passive elements. All the five filter responses, i.e., high-pass, low-pass, band-pass, band-stop, and all-pass responses, are obtained from the same circuit topology. Moreover, the pole frequency and quality factor are independently tunable. Additionally, they do not require any double/inverted input signals for response realization. Furthermore, they enjoy low active and passive sensitivities. Various regular analyses support the design ideas. The functionality of the presented filters are tested by PSPICE simulations using TSMC 0.18 µm technology parameters with ± 0.9 V supply voltage. The circuits are also justified experimentally by creating the VDCC block using commercially available OPA860 ICs. The experimental and simulation results agree well with the theoretically predicted results

Biosorption of Acid dye by Jackfruit Leaf Powder: Isotherm, kinetics and Response surface methodology studies

A green adsorbent derived from Jackfruit leaf powder (JLP) was used to eliminate Acid Yellow 99 (AY 99) dye from an aqueous medium in this study. We checked the effect of pH, biomass dosage, and temperature (process parameters) on the adsorption potential of AY 99 was explored using the CCD model integrating the RSM approach. At a pH of 2.5, biosorbent dosage of 4 gL-1, and a 30°C temperature, maximum removal was preferred. ANOVA was incorporated to observe the importance of experimental variables and their interactions. The solution pH (A) and biomass dose (C) had the greatest effects on the decolorization of AY 99, according to the findings. ANOVA was used to identify the most important factors, which included two independent variables (A and C) and two quadratic model terms (A2 and C2). The kinetic data were effectively interpreted using a pseudo 2nd order with film diffusion model combination, indicating the chemisorptions phenomenon. Following the model of Langmuir isotherm, the utmost capacity for adsorption was determined to be 418.15 mg g-1 in terms of initial dye concentration. The findings of the maximum adsorption capacity showed that JLP could be employed as a useful adsorbent to eliminate AY 99 from its aqueous medium

Lossy & Lossless Capacitance Multipliers: A Series of Realization Using VDTAs & Single Grounded Capacitor

The article presents new realizations of capacitance multiplier circuits, employing two voltage differencing transconductance amplifiers (VDTAs) and one capacitor without any passive resistors. The equivalent capacitance value of the proposed capacitance simulators can be achieved electronically by regulating the DC bias currents of VDTAs. All the proposed realizations do not require any critical component matching conditions. The lossless floating negative capacitor multiplier (NCM) circuit is studied in detail. The capacitive cancellation scheme and a quadrature sinusoidal oscillator circuit are included to demonstrate the effectiveness of the circuit. The effect of the VDTA non-idealities and parasitic on the realized circuits is analysed. SPICE simulation results using TSMC 0.18 μm CMOS technology parameters are presented to reflect the workability of the proposed NCM