Fixed-point MAP decoding of channel codes

This paper describes the fixed-point model of the maximum a posteriori (MAP) decoding algorithm of turbo and low-density parity-check (LDPC) codes, the most advanced channel codes adopted by modern communication systems for forward error correction (FEC). Fixed-point models of the decoding algorithms are developed in a unified framework based on the use of the Bahl-Cocke-Jelinek-Raviv (BCJR) algorithm. This approach aims at bridging the gap toward the design of a universal, multistandard decoder of channel codes, capable of supporting the two classes of codes and having reduced requirements in terms of silicon area and power consumption and so suitable to mobile applications. The developed models allow the identification of key parameters such as dynamic range and number of bits, whose impact on the error correction performance of the algorithm is of pivotal importance for the definition of the architectural tradeoffs between complexity and performance. This is done by taking the turbo and LDPC codes of two recent communication standards such asWiMAX and 3GPP-LTE as a reference benchmark for a mobile scenario and by analyzing their performance over additive white Gaussian noise (AWGN) channel for different values of the fixed-point parameters

Ambient Assisted Living and Ageing: Preliminary Results of RITA Project

The ageing of population is a social phenomenon that most of worldwide countries are facing. They are, and will be even more in the future, indeed trying to find solutions for improving quality of life of their elderly citizens. The project RITA wants to demonstrate that an update of the current socio-medical services with an Ambient Assisted Living (AAL) approach could improve the service efficiency and the quality of life of both elderly and caregiver. This paper presents the preliminary results obtained in RITA

A Flexible State-Metric Recursion Unit for a Multi-Standard BCJR Decoder

This paper describes the architecture of a flexible and reconfigurable processor for the computation of the state-metric recursion in a multi-standard BCJR decoder. The unit can serve binary as well as duo-binary codes with any number of states. The architecture is arranged into a cluster of state-metric processors plus two multiplexing networks for feedback and normalization, configured on-the-fly for the code in use. An optimized solution is presented allowing the support of every code among 8-state duo-binary, 8-state binary and 2-state binary codes, i.e., of every Turbo and LDPC code defined by the modern communication standards. The logical synthesis on different CMOS technologies shows that the architecture attains a maximum clock frequency of 450 MHz. Finally, the complexity overhead of such a flexible design is only about 18% w.r.t. optimized single-standard solutions

A Multi-Standard Flexible Turbo/LDPC Decoder via ASIC Design

This paper describes the first complete design of a single-core multi-standard flexible Turbo/LDPC decoder using an ASIC approach. Such a solution outperforms other state-of-the-art implementations based on application-specific instruction-set processors (ASIPs), which are shown to sufTer from impaired throughput and power consumption. In this paper, we describe in detail the VLSI flexible architecture of a decoder coping with all the moderu communication standards defining LDPC and Turbo codes, and provide a proof-of-concept implementation complaint with 3GPP-HSDPA, DVB-SH, IEEE 802.16e and IEEE 802.11n standards. The decoder, running at only 150 MHz for a reduced power, occupies an area of 0.9mm2 with a maximum power consumption of only 86.1 mW

Low-Power Techniques for Flexible Channel Decoders

This paper proposes a framework for a low-power design of flexible multi-standard channel decoders which are the most computational demanding blocks of modern communication systems. A power-efficient design envisages hardware level techniques to reduce static power consumption and algorithmic level technique to early stop the iterative decoding when the received information is estimated to be correct. Particularly, the paper focuses on two different stopping rules for Turbo codes which are well-suited for a multi-standard scenario. Simulation results indeed show an achievable power saving ranging from 50% to 80%

Low-Complexity Architectures of a Decoder for IEEE 802.16e LDPC Codes

Low-density parity-check (LDPC) codes have recently been included as error-correcting codes in IEEE 802.16e, for wireless metropolitan area networks. This paper proposes a flexible, low-complexity LDPC decoder fully compliant with all 114 codes defined by the standard. The decoder runs the layered decoding algorithm to increase the convergence speed, and relies on a semi-parallel implementation with serial processing units working in pipeline to reduce the latency. Particularly, two different architectures are considered, and their RTL/memory complexity tradeoffs are analyzed. The resulting design yields a throughput ranging from 93 to 497 Mbps by means of 15 iterations at the clock frequency of 400 MHz. Synthesis on 65 nm CMOS technology, shows a chip area less than 0.59 mm2, despite the high flexibility, which compares favourably with similar implementations

Techniques and Architectures for Hazard-Free Semi-Parallel Decoding of LDPC Codes

The layered decoding algorithm has recently been proposed as an efficient means for the decoding of low-density parity-check (LDPC) codes, thanks to the remarkable improvement in the convergence speed (2x) of the decoding process. However, pipelined semi-parallel decoders suffer from violations or hazards between consecutive updates, which not only violate the layered principle but also enforce the loops in the code, thus spoiling the error correction performance. This paper describes three different techniques to properly reschedule the decoding updates, based on the careful insertion of idle cycles, to prevent the hazards of the pipeline mechanism. Also, different semi-parallel architectures of a layered LDPC decoder suitable for use with such techniques are analyzed. Then, taking the LDPC codes for the wireless local area network (IEEE 802.11n) as a case study, a detailed analysis of the performance attained with the proposed techniques and architectures is reported, and results of the logic synthesis on a 65nm low-power CMOS technology are shown