Study of self-limiting oxidation of silicon nanoclusters by atomistic simulations

International audienc

Echangeur compact performant nettoyable cote externe a serpentins integres: qualification thermique

SIGLECNRS RP 400 (1004) / INIST-CNRS - Institut de l'Information Scientifique et TechniqueFRFranc

Etude de l'influence de la turbulence amont sur les performances thermiques d'un faisceau de tubes ailetes peu profond et permeable

SIGLEAvailable at INIST (FR), Document Supply Service, under shelf-number : AR 13978 / INIST-CNRS - Institut de l'Information Scientifique et TechniqueFRFranc

Implantation and epitaxial effects on strained-Silicon-on-Insulator transport Com. a 2006 European Materials Research Society Meeting, Symposium B ‘From Strained

International audienc

Er-doped light emitting slot waveguides monolithically integrated in a silicon photonic chip

An integrated erbium-based light emitting diode has been realized in a waveguide configuration allowing 1.54 μm light signal routing in silicon photonic circuits. This injection device is based on an asymmetric horizontal slot waveguide where the active slot material is Er(3+) in SiO2 or Er(3+) in Si-rich oxide. The active horizontal slot waveguide allows optical confinement, guiding and lateral extraction of the light for on-chip distribution. Light is then coupled through a taper section to a passive Si waveguide terminated by a grating which extracts (or inserts) the light signal for measuring purposes. We measured an optical power density in the range of tens of μW/cm(2) which follows a super-linear dependence on injected current density. When the device is biased at high current density, upon a voltage pulse (pump signal), free-carrier and space charge absorption losses become large, attenuating a probe signal by more than 60 dB/cm and thus behaving conceptually as an electro-optical modulator. The integrated device reported here is the first example, still to be optimized, of a fundamental block to realize an integrated silicon photonic circuit with monolithic integration of the light emitter

Mechanical simulation of stress engineering solutions in highly strained p-type FDSOI MOSFETs for 14-nm node and beyond

International audienceStress engineering is a powerful tool to enhance nanoscale device performances. In this study we developed a methodology of 14nm strained pMOS FDSOI device mechanical simulation in order to carefully evaluate different stress effects on device performances. Mechanical simulation results are presented for different process solutions, such as Gate-First (GF) and Gate-Last (GL) processes but also for variation of germanium contents in source/drain and channel regions

2D TCAD strain simulations from fully depleted to nanowire transistors: efficiency of mechanical stressors

session posterInternational audienc

Carrier mobility degradation due to high dose implantation in ultrathin unstrained and strained silicon-on-insulator films

International audienc