Efficient Hardware Design for Computing Pairings Using Few FPGA In-built DSPs

This paper is devoted to the design of a 258-bit multiplier for computing pairings over Barreto-Naehrig (BN) curves at 128-bit security level. The proposed design is optimized for Xilinx field programmable gate array (FPGA). Each 258-bit integer is represented as a polynomial with five, 65 bit signed integer, coefficients. Exploiting this splitting we designed a pipelined 65-bit multiplier based on new Karatsuba- Ofman variant using non-standard splitting to fit to the Xilinx embedded digital signal processor (DSP) blocks. We prototype the coprocessor in two architectures pipelined and serial on a Xilinx Virtex-6 FPGA using around 17000 slices and 11 DSPs in the pipelined design and 7 DSPs in the serial. The pipelined 128-bit pairing is computed in 1. 8 ms running at 225MHz and the serial is performed in 2.2 ms running at 185MHz. To the best of our knowledge, this implementation outperforms all reported hardware designs in term of DSP use. Keywords

A Novel Multispectral Lab-depth based Edge Detector for Color Images with Occluded Objects

International audienceThis paper presents a new method for edge detection based on both Lab color and depth images. The principalchallenge of multispectral edge detection consists of integrating different information into one meaningfulresult, without requiring empirical parameters. Our method combines the Lab color channels and depth information in a well-posed way using the Jacobian matrix. Unlike classical multi-spectral edge detection methods using depth information, our method does not use empirical parameters. Thus, it is quite straightforward and efficient. Experiments have been carried out on Middlebury stereo dataset and several selected challenging images. Experimental results show that the proposed method outperforms recent relevant state-of-the-art methods

A novel multispectral corner detector and a new local descriptor: an application to human posture recognition

International audienceHuman posture recognition is an important task for intelligent systems specially those performing action recognition. In this paper, we propose a novel multispectral corner detector and a new HOG-based multispectral local descriptor. First, we select salient features which are extracted from an edge image obtained by picking the maximum eigenvalue of the jacobian matrix. Second, we extract for each feature point a local descriptor which combines both the Lab colour channels and depth information in a well-posed way using the Jacobian matrix. Last, we conduct a one-against-all learning strategy using both an incremental Covariance-guided One-Class Support Vector Machine (iCOSVM) and a Convolutional Neural Network (CNN). Experimental results show that we outperform the state-of-the-art methods whether our descriptor is combined with iCOSVM and with CNN

Efficient Multiplier for pairings over Barreto-Naehrig Curves on Virtex-6 FPGA

Abstract—This paper is devoted to the design of a 258bit multiplier for computing pairings over Barreto-Naehrig (BN) curves at 128-bit security level. The proposed design is optimized for Xilinx field programmable gate array (FPGA). Each 258-bit integer is represented as a polynomial with five, 65 bit signed integer, coefficients. Exploiting this splitting we designed a pipelined 65-bit multiplier based on new Karatsuba-Ofman variant using non-standard splitting to fit to the Xilinx embedded digital signal processor (DSP) blocks. Our architecture is able to compute 258-bit multiplication suitable for BN curves using only 11 in-built DSP blocks available on Virtex-6 Xilinx FPGA devices. It is the least DSP blocks consumption in the known literature. This work can be extended to efficiently compute pairings at higher security levels