INTRODUCING AN OPTIMAL QCA CROSSBAR SWITCH FOR BASELINE NETWORK

Crossbar switch is the basic component in multi-stage interconnection networks. Therefore, this study was conducted to investigate performance of a crossbar switch with two multiplexers. The presented crossbar switch was simulated using quantum-dot cellular automata (QCA) technology and QCA Designer software, and was studied and optimized in terms of cell number, occupied area, number of clocks, and energy consumption. Using the provided crossbar switch, the baseline network was designed to be optimal in terms of cell number and occupied area. Also, the number of input states was investigated and simulated to verify accuracy of the baseline network. The proposed crossbar switch uses 62 QCA cells and the occupied area by the switch is equal to 0.06µm2 and its latency equals 4 clock zones, which is more efficient than the other designs. In this paper, using the presented crossbar switch, the baseline network was designed with 1713 cells, and occupied area of 2.89µm2

STUDY OF HOLE-BLOCKING AND ELECTRON-BLOCKING LAYERS IN A InAs/GaAs MULTIPLE QUANTUM-WELL SOLAR CELL

In this work, a GaAs-based quantum well solar cell with a 25-layer InAs/GaAs intermediate layer is simulated in Silvaco Atlas TCAD software. In order to reduce the recombination caused by the presence of the quantum layers and increase the absorption of photons, electron blocking layers (EBLs) and hole blocking layers (HBLs) have been added to the solar cell in an In0.5(Al0.7Ga0.3)0.5P semiconductor. The results show that the efficiency of the proposed solar cell increases 17.38% by obtaining impurity the thickness and doping of the EBL and HBL layers. It can be concluded that the use of the In0.5(Al0.7Ga 0.3)0.5P semiconductor with EBL and HBL layers decreases the open circuit voltage (Voc) caused in the quantum wells. The efficiency of the proposed solar cell with EBL and HBL layers was found to be 44.65%

CHAOTIC SEISMIC SIGNAL MODELING BASED ON NOISE AND EARTHQUAKE ANOMALY DETECTION

Since ancient times, people have tried to predict earthquakes using simple perceptions such as animal behavior. The prediction of the time and strength of an earthquake is of primary concern. In this study chaotic signal modeling is used based on noise and detecting anomalies before an earthquake using artificial neural networks (ANNs). Artificial neural networks are efficient tools for solving complex problems such as prediction and identification. In this study, the effective features of chaotic signal model is obtained considering noise and detection of anomalies five minutes before an earthquake occurrence. Neuro-fuzzy classifier and MLP neural network approaches showed acceptable accuracy of 84.6491% and 82.8947%, respectively. Results demonstrate that the proposed method is an effective seismic signal model based on noise and anomaly detection before an earthquake

INTRODUCING A NOVEL HIGH-EFFICIENCY ARC LESS HETEROUNCTION DJ SOLAR CELL

The present study was undertaken to examine the structure and performance of hetero junctions on the fill factor, short circuit current and open circuit voltage of aInGaP/GaAsdual-junction solar cell. This goal of this work was to reduce recombination in the bottom cell so that the electrons and holes produced in the top cell with the lowest recombination participate in the output current. Semiconductors with a high bandwidth from the ѵш group were studied in order to obtain a high open circuit voltage. By observing mobility and lattice constant semiconductors (Al0.52In0.48P, GaAs and In0.49Ga0.51P), it was concluded that the semiconductor Al0.52In0.48P has high electron mobility and hole mobility and that the lattice constant matched to the GaAs semiconductor can be effective in reducing recombination. The cathode current and absorbed photons show that the composition InGaP/AlInP increased the number of charge carriers in the top cell. The structure of InGaP-AlInP/GaAs-AlInP was obtained by inserting an InGaP-AlInP heterojunction at the top and GaAs-AlInP heterojunction at the bottom of aInGaP/GaAs dual-junction cell. For this structure, short circuit current (JSC)  = 22.96 mA/cm2, open circuit voltage (Voc) = 2.72 V, fill factor (FF) = 93.26% and efficiency(η)= 58.28% were obtained under AM1.5 (1 sun) of radiation

A Novel De Bruijn Based Mesh Topology for Networks-on-Chip

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Diseño de sumador completo rápido de baja potencia utilizando Domino Logic basado en Unión de Túnel Magnético (UTM) y Memristor

Los circuitos CMOS de Domino se utilizan ampliamente en sistemas integrados de gran escala (VLSI) de alto rendimiento. La topología de los circuitos dominó para operación de alta velocidad, menor consumo de energía y robustez es de gran importancia en el diseño de sistemas digitales. El presente artículo propone un circuito sumador completo de baja potencia y alta velocidad, que utiliza una nueva familia lógica de dominó CMOS basada en elementos de unión de túnel magnético (UTM) y memristor en la técnica de entrada de difusión de puerta (GDI). En comparación con un circuito lógico CMOS estático, un circuito lógico dinámico es importante ya que proporciona una mayor velocidad y requiere menos transistores. En comparación con los circuitos propuestos recientemente para estilos lógicos dinámicos, las características del circuito propuesto son un consumo de energía dinámica muy bajo y menos retardo. El problema con los circuitos dinámicos es la falta de una salida estable en diferentes momentos, mientras que el circuito propuesto conserva el valor de salida utilizando elementos de memoria como UTM y memristor durante el ciclo de reloj. La técnica propuesta muestra un consumo máximo de energía de 0,317 µW en sumadores completos basados en MTJ/Memristor. Además, la técnica propuesta muestra un retraso máximo de 0,35 ns. Se simula el sumador completo propuesto, y su disipación de potencia y rendimiento se analizan utilizando HSPICE en tecnología CMOS estándar de 7 nm

Two Novel Quantum-Dot Cellular Automata Full Adders

Quantum-dot cellular automata (QCA) is an efficient technology to create computing devices. QCA is a suitable candidate for the next generation of digital systems. Full adders are the main member of computational systems because other operations can be implemented by adders. In this paper, two QCA full adders are introduced. The first one is implemented in one layer, and the second one is implemented in three layers. Five-input majority gate is used in both of them. These full adders are better than pervious designs in terms of area, delay, and complexity