31st Annual Meeting and Associated Programs of the Society for Immunotherapy of Cancer (SITC 2016) : part two

Background The immunological escape of tumors represents one of the main ob- stacles to the treatment of malignancies. The blockade of PD-1 or CTLA-4 receptors represented a milestone in the history of immunotherapy. However, immune checkpoint inhibitors seem to be effective in specific cohorts of patients. It has been proposed that their efficacy relies on the presence of an immunological response. Thus, we hypothesized that disruption of the PD-L1/PD-1 axis would synergize with our oncolytic vaccine platform PeptiCRAd. Methods We used murine B16OVA in vivo tumor models and flow cytometry analysis to investigate the immunological background. Results First, we found that high-burden B16OVA tumors were refractory to combination immunotherapy. However, with a more aggressive schedule, tumors with a lower burden were more susceptible to the combination of PeptiCRAd and PD-L1 blockade. The therapy signifi- cantly increased the median survival of mice (Fig. 7). Interestingly, the reduced growth of contralaterally injected B16F10 cells sug- gested the presence of a long lasting immunological memory also against non-targeted antigens. Concerning the functional state of tumor infiltrating lymphocytes (TILs), we found that all the immune therapies would enhance the percentage of activated (PD-1pos TIM- 3neg) T lymphocytes and reduce the amount of exhausted (PD-1pos TIM-3pos) cells compared to placebo. As expected, we found that PeptiCRAd monotherapy could increase the number of antigen spe- cific CD8+ T cells compared to other treatments. However, only the combination with PD-L1 blockade could significantly increase the ra- tio between activated and exhausted pentamer positive cells (p= 0.0058), suggesting that by disrupting the PD-1/PD-L1 axis we could decrease the amount of dysfunctional antigen specific T cells. We ob- served that the anatomical location deeply influenced the state of CD4+ and CD8+ T lymphocytes. In fact, TIM-3 expression was in- creased by 2 fold on TILs compared to splenic and lymphoid T cells. In the CD8+ compartment, the expression of PD-1 on the surface seemed to be restricted to the tumor micro-environment, while CD4 + T cells had a high expression of PD-1 also in lymphoid organs. Interestingly, we found that the levels of PD-1 were significantly higher on CD8+ T cells than on CD4+ T cells into the tumor micro- environment (p < 0.0001). Conclusions In conclusion, we demonstrated that the efficacy of immune check- point inhibitors might be strongly enhanced by their combination with cancer vaccines. PeptiCRAd was able to increase the number of antigen-specific T cells and PD-L1 blockade prevented their exhaus- tion, resulting in long-lasting immunological memory and increased median survival

Reliability and Testing of Complex Safety-Critical Automotive SoC

L'abstract è presente nell'allegato / the abstract is in the attachmen

An Evolutionary Approach to Hardware Encryption and Trojan-Horse Mitigation

New threats, grouped under the name of hardware attacks, became a serious concern in recent years. In a global market, untrusted parties in the supply chain may jeopardize the production of integrated circuits with intellectual-property piracy, illegal overproduction, and hardware Trojan-horses injection. While one way to protect from overproduction is to encrypt the design by inserting logic gates that prevents the circuit from generating the correct outputs unless the right key is used, reducing the number of poorly-controllable signals is known to minimize the chances for an attacker to successfully hide the trigger for some malicious payload. Several approaches successfully tackled independently these two issues. Differently, this paper proposes a novel technique based on a multi-objective evolutionary algorithm able to increase hardware security by explicitly targeting both the minimization of rare signals and the maximization of the efficacy of logic encryption. Experimental results demonstrate the effectiveness of the proposed method

On-Line Software-based Self-Test for ECC of Embedded RAM Memories

Error Correcting Code (ECC) techniques aims at providing concurrent correction and detection of single and multiple faults that can affect the memory array. The literature largely discusses how to protect the memory content with ECC codes. In this paper, we discuss about faults affecting the ECC logic in charge of encode and decode the ECC codes. It is a common perception that faults in such a calculation unit can only rise the occurrence of false positive behaviors. This assumption is not always true because some latent faults require a careful excitation sequence, including intentional corruption of the memory content to verify detection and correction ability. The manuscript provides a complete taxonomy of failing behaviors. Furthermore, it illustrates how to generate a proper flow of memory accesses to be finally translated into a Software-Based Self-Test (SBST) program. The paper provides an automotive case of study by STMicroelectronics; the analyzed ECC logic implements a Single Error Correction Double Error Detection (SEC-DEC) to protect RAM memories. The proposed method achieves the 93% over around 30K stuck-at faults and the generated SBST test program length is around 0.5 ms at a 128MHz system frequency

Defeating Hardware Trojan through Software Obfuscation

In recent years a new kind of threat, known as Hard- ware Trojan, is affecting the Integrated Circuit industry. Due to the segmentation in the production, untrusted parties involved in the supply chain may illegally inject additional hardware components, that, under specific circumstances, act for malicious purposes. While it is mostly unfeasible to identify malicious hardware tampering with in-lab testing, as a remedy, several countermeasures have been proposed, mostly based on hardware alterations of the original design, with the main drawbacks of in- creased production costs, increased area and energy consumption. In this paper, we introduce a cost effective solution, completely software-based, that minimize the chance of activation of a multi- stage trigger Hardware Trojan. The proposed approach relies on a software obfuscation mechanism, which exploits evolutionary algorithms to modify an executable program without affecting its original functionalities. Such always-changing, obfuscation routine, can be used to protect critical infrastructures and operations, at a minimum and predictable loss of performances. To show the effectiveness of the proposed technique, we developed a proof-of-concept evolutionary obfuscator and we are going to test it against a well-known real-world hardware attack scenario

Scan chain encryption for the test, diagnosis and debug of secure circuits

Scan attacks exploit facilities offered by scan chains to retrieve embedded secret data, in particular secret keys used in crypto-processors for encoding information in such a way that only knowledge of the secret key allows to access it. This paper presents a scan attack countermeasure based on the encryption of the scan chain content. The goal is to counteract the security threats and, at the same time, to preserve test efficiency, diagnosis and debugging abilities. We propose to use the secret-key management policy embedded in the device under test in order to encrypt both control and observed data at test time. This solution does not require additional key management, provides same test/diagnostic and debug facilities as under classical scan design with marginal impacts on area and test time

A DMA and CACHE-based stress schema for burn-in of automotive microcontroller

Thermal and electrical stress phases are commonly applied to automotive devices at the end of manufacturing test to give rise to early life latent failures. This paper proposes a new methodology to optimize the stress procedures during the Burn-In phase. In the proposed method, stress of CPU, RAM memory and FLASH memory are run in parallel using DMA and CACHE interventions. The paper reports also some experimental results gathered in an automotive microcontroller, and a comparison between traditional and parallelized burn-in stress technique is also provided

Adaptive Management Techniques for Optimized Burn-In of Safety-Critical SoC

The cost of Burn-In is a major concern for the testing of Automotive Systems-on-Chip (SoC). This paper highlights problematic aspects of a Burn-In flow and describes a two-layered adaptive technique that permits to optimize the stress application and strongly reduce BI test time. At the SoC level, the described methodology adaptively copes with FLASH erase time uncertainties; at the Automatic Test Equipment (ATE) level, the strategy relies on power monitors and tester intelligence. The paper reports experimental results on a SoC manufactured by STMicroelectronics; figures show an optimized usage of stress resources and demonstrates a reduction of 25% of the BI test time when using the proposed adaptive techniques