Fast clock tree generation using exact zero skew clock routing algorithm

A Zero Skew clock routing methodology has been developed to help design team speed up their clock tree generation process. The methodology works by breaking up the clock net into smaller partitions, then inserting clock buffers to drive each portion and lastly, routing the connection from original clock source to each newly inserted clock buffers with zero skew. A few Perl scripts and a new visual basic based routing tool have been developed to support the methodology implementation. The routing algorithm used in this tool is based on the Exact Zero Skew Routing Algorithm. The methodology has been tested using a real design database and resulting in a significant improvement in the through put time required to complete the clock tree generation. This improvement is attributed to the ability to generate clock tree on much smaller portions of clock nets that supports of speeding up the clock tree generation process in IC design

Design and application of radio frequency identification systems

The recent world, development of effective technologies for linking the object wireless information is being prompted in various fields. Radio frequency identification (RFID) is the latest technology for automatic identification which allows the transmission of a unique serial number wirelessly. The purpose of this paper is to review RFID systems and its various components infrastructure. The components and features are still under research and being integrated in existing systems to create a marketable and potential new system. To achieve higher performance; low cost, low power RFID tag with efficient anticollision technique which provides a large throughput and flexible security mechanism is required. The review has shown different types of readers, antennas and tags which would becomes a bottleneck to reduce the RFID cost. The paper has shown details the entire components where RFID researchers will get benefit for the development of future technology. The challenges of RFID system design with the entire components (Reader, Tag and Antenna) and its advantages, disadvantages are briefly explained

Zero skew clock routing for fast clock tree generation

A Zero Skew Clock Routing Methodology has been developed to help design team speed up their clock tree generation process. The methodology works by breaking up the clock net into smaller partitions, then inserting clock buffers to drive each portion, and lastly, routing the connection from original clock source to each newly inserted clock buffers with zero skew. A few Perl scripts and a new Visual Basic based routing tool have been developed to support the methodology implementation. The routing algorithm used in this tool is based on the Exact Zero Skew Routing Algorithm. The methodology has been tested using a real design database and resulting in a significant improvement in the through put time required to complete the clock tree generation. This improvement is attributed to the ability to generate clock tree on much smaller portions of clock nets that supports of speeding up the clock tree generation process in IC design

Techniques of FECG signal analysis: detection and processing for fetal monitoring

Fetal heart rate monitoring is a technique for obtaining important information about the condition of a fetus during pregnancy and labor, by detecting the FECG signal generated by the heart of the fetus. The ultimate reason for the interest in FECG signal analysis is in clinical diagnosis and biomedical applications. The extraction and detection of the FECG signal from composite abdominal signals with powerful and advance methodologies is becoming a very important requirement in fetal monitoring. The purpose of this review paper is to illustrate the various methodologies and algorithms on FECG signal detection and analysis to provide efficient and effective ways of understanding the FECG signal and its nature. A comparative study has been carried out to show the performance of various methods. This paper opens up a passage to biomedical researchers, physicians and end users to advocate an excellent understanding of FECG signal and its analysis procedures for fetal heart rate monitoring system by providing valuable information to help them in developing more dominant, flexible and resourceful application

Hardware prototyping of an efficient encryption engine

An approach to develop the FPGA of a flexible key RSA encryption engine that can be used as a standard device in the secured communication system is presented. The VHDL modeling of this RSA encryption engine has the unique characteristics of supporting multiple key sizes, thus can easily be fit into the systems that require different levels of security. A simple nested loop addition and subtraction have been used in order to implement the RSA operation. This has made the processing time faster and used comparatively smaller amount of space in the FPGA. The hardware design is targeted on Altera STRATIX II device and determined that the flexible key RSA encryption engine can be best suited in the device named EP2S30F484C3. The RSA encryption implementation has made use of 13,779 units of logic elements and achieved a clock frequency of 17.77MHz. It has been verified that this RSA encryption engine can perform 32-bit, 256-bit and 1024-bit encryption operation in less than 41.585us, 531.515us and 790.61us respectively

FPGA implementation of RSA encryption engine with flexible key size

An approach to develop the FPGA of a flexible key RSA encryption engine that can be used as a standard device in the secured communication system is presented. The VHDL modeling of this RSA encryption engine has the unique characteristics of supporting multiple key sizes, thus can easily be fit into the systems that require different levels of security. A simple nested loop addition and subtraction have been used in order to implement the RSA operation. This has made the processing time faster and used comparatively smaller amount of space in the FPGA. The hardware design is targeted on Altera STRATIX II device and determined that the flexible key RSA encryption engine can be best suited in the device named EP2S30F484C3. The RSA encryption implementation has made use of 13,779 units of logic elements and achieved a clock frequency of 17.77MHz. It has been verified that this RSA encryption engine can perform 32-bit, 256-bit and 1024-bit encryption operation in less than 41.585us, 531.515us and 790.61us respectively

EEG signal analysis and characterization for the aid of disabled people

The effectiveness of assistive devices for disabled people is often limited by the human machine interface. This research proposes an intelligent wheelchair system especially for severely disabled people based on analysing electroencephalographic signals by using discrete wavelet transform and higher order statistical methods. The system to be implemented in Field Programmable Gate Array enables an accurate and efficient system of processing signals to control the wheelchair, which makes an attractive option in the hardware realization

Fetal QRS complex Detection Algorithm for FPGA Implementation

An algorithm has been developed for the simultaneous measurement of the fetal and maternal heart rates from the maternal abdominal electrocardiogram during pregnancy and labor for fetal monitoring. The algorithm is based on crosscorrelation, adaptive thresholding and statistical properties in the time domain. Hardware description language - VHDL has been used to implement the algorithm for FPGA implementation. The design is synthesized and fitted into Altera’s Stratix EP1S10 using the Quartus II platform. Test case results showed an error percentage of around ±0.3% and ±0.5% for the detection of maternal and fetal heart rate respectively