Characterization of electrostatic discharge threshold voltage of phase-shift mask reticle

A reticle is a stencil used in lithography process for forming integrated circuit (IC) on silicon substrate. It consists of a thin (100 nm) coating of masking metallic patterned (features) with critical dimension (CD) of nanometers on a thicker quartz substrate. The features can be damaged by electrostatic discharge (ESD) when exposed to the environment electrostatic charge and caused deformed IC and eventually device difunctional. Semiconductor equipment materials industry (SEMI) standard established the allowable electrostatic charge on reticle based on the characterization of ESD threshold voltage on binary reticle. However, there is another type of reticle which is phase-shift mask (PSM), has not been characterized for its ESD threshold voltage. A direct current (DC) voltage is applied directly to the structures with CD of 80 nm, 110 nm, and 160 nm. The surface current is recorded at all levels of stress from 1 to 100 V. The current–voltage (IV) curve and physical inspection results for each cell are then reviewed and classified. The results yielded which no electric field induced migration (EFM) defect and breakdown voltage occurred at any of the structures. The cathode’s metal work function has been identified as the factor that influences the PSM reticle ESD threshold voltage

Experimental quantification of electrostatic damage (ESD) in binary reticle with feature of nanometre scale gaps

A Binary reticle for lithography circuit patterning is extremerly senstive to electrostatic field. Damaged is seen on its feature after a breakdown voltage occurred between the metal lines. The experimental quantification of ESD for Binary reticle is performed by direct discharge to the feature of Critical Dimension (CD) of 80 nm to 160 nm. Its breakdown voltage correlated to CD but lower than international standard recommendations and observed Electric Field-Induced Migration (EFM) damaged at CD of 110 nm to 160 nm

Characterization of electrostatic discharge threshold voltage of phase-shift mask reticle

A reticle is a stencil used in lithography process for forming integrated circuit (IC) on silicon substrate. It consists of a thin (100 nm) coating of masking metallic patterned (features) with critical dimension (CD) of nanometers on a thicker quartz substrate. The features can be damaged by electrostatic discharge (ESD) when exposed to the environment electrostatic charge and caused deformed IC and eventually device difunctional. Semiconductor equipment materials industry (SEMI) standard established the allowable electrostatic charge on reticle based on the characterization of ESD threshold voltage on binary reticle. However, there is another type of reticle which is phase-shift mask (PSM), has not been characterized for its ESD threshold voltage. A direct current (DC) voltage is applied directly to the structures with CD of 80 nm, 110 nm, and 160 nm. The surface current is recorded at all levels of stress from 1 to 100 V. The current–voltage (IV) curve and physical inspection results for each cell are then reviewed and classified. The results yielded which no electric field induced migration (EFM) defect and breakdown voltage occurred at any of the structures. The cathode’s metal work function has been identified as the factor that influences the PSM reticle ESD threshold voltage

A Preliminary Study Of Characterization Techniques For Reticle ESD Threshold Voltage Measurement

Recent studies have revealed that reticle robustness towards electrostatic field is reducing since the feature’s critical dimension is getting smaller. Reticle electrostatic damage is seen after the features was subjected at low Electrostatic Discharged (ESD) voltages. This characterization was conducted on a Chrome-on-glass (COG)/Binary reticle metal layer for Complementary Metal Oxide Semiconductor (CMOS) 250nm technology node. International Technology Roadmap for Semiconductor (ITRS) and Semiconductor Equipment and Materials International (SEMI) uses the results of this reticle electrostatic damaged characterization, extrapolates it and establishes electrostatic field limits for semiconductor industry. Generally, a semiconductor wafer fabrication company will refer to this guideline to set up an Electrostatic Protective Area (EPA) for the expansion of current facilities or new facilities. As CMOS technology node shrinks further to 130nm, the photolithography process becomes more challenging since it requires printing smaller features accurately. A newly advanced reticle, called PSM (Phase-shift Mask) reticle has been introduced. PSM reticle features are made of Molybdenum Silicide (MoSi) material, which is different from the Binary reticle that uses Chromium. Existing guideline for electrostatic control limit from ITRS and SEMI may not be sufficient to protect PSM reticle from ESD damaged due to the different material features and the smaller critical dimension (gap distance between two parallel lines). This paper proposed a future work for characterizing PSM reticle ESD threshold voltage measurement and documented the result in ITRS and SEMI as separate guideline. This study will benefit semiconductor industry to implement more accurate EPA according to reticle type and technology node. The previous characterization techniques will be reviewed and critically compared in order to gain a better understanding of the reticle ESD damaged mechanism and propose new techniques for characterizing reticle that reflect actual production environment, the latest features material and lower technology node