CHASSIS : a combined hardware selection and scheduling technique for performance driven synthesis

This report describes a new technique that combines the Hardware Scheduling and Component Selection phases for High Level Synthesis. Our technique simultaneously selects components from a given library while it schedules the operations into different control steps. The algoríthm improves previous work in scheduling because component costs and performance are considered during the scheduling process, enlarging the design search space and resulting in better optimized desígns

VHDL synthesis system (VSS) : user's manual, version 5.0

This report provides instructions for installing and using the VHDL Synthesis System (Version 5.0). VSS is a high level synthesis sytem that synthesizes structures from an abstract description, written with VHDL behavioral constructs. The system uses components from a generic component library (GENUS). The output of VSS is in structural VHDL and could be verified using a commercial VHDL simulator. The designer can control the synthesis process by providing different resource constraints to the system. VSS is also capable of producing different architectures which can be selected by the designer

Semantics and synthesis of signals in behavioral VHDL

Signals are a fundamental part of VHDL behavioral descriptions. There are many kinds of VHDL signals, each possesing complex and hence often misunderstood semantics. The result is that synthesis tools often inadequately address synthesis of signals. In this report, we first make clear the semantics of the various signal kinds shared by multiple processes through the use of conceptual hardware, rather than just text. Second, with the semantics firmly understood, we discuss techniques and issues in synthesizing actual hardware for shared signals. This information can be used to take a step towards synthesizing correct hardware from VHDL descriptions while greatly reducing current restrictions imposed by synthesis tools on allowable VHDL behavior

Architectural Tradeoffs in Synthesis of Pipelined Controls

Many high level synthesis systems produce designs without any consideration for the underlying architecture. In such systems, tradeoffs between area and delay can only be achieved by changing the synthesis constraints (e.g., number of functional units). These systems do not exploit the wider range of tradeoffs that can be achieved by modifying the underlying architecture. In this report we derive a relationship between architectural constraints and scheduling algorithms, and demonstrate how architectural styles impose certain restrictions on the scheduling process. In particular, we consider different control pipelining architectures. We also propose a versatile scheduling algorithm that is capable of synthesising designs for different control pipelining styles. Contents 1 Introduction 1 2 Control Pipelined Architectures 2 2.1 Non-pipelined methodology : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 4 2.1.1 Status Pipelined Methodology : : : : : : : : ..

CHASSIS : a combined hardware selection and scheduling technique for performance driven synthesis

This report describes a new technique that combines the Hardware Scheduling and Component Selection phases for High Level Synthesis. Our technique simultaneously selects components from a given library while it schedules the operations into different control steps. The algoríthm improves previous work in scheduling because component costs and performance are considered during the scheduling process, enlarging the design search space and resulting in better optimized desígns

Behavioral design assistant (BdA) user's manual : version 1.0

This report provides instructions for installing and using the Behavioral Design Assistant (BdA). BdA is a behavioral synthesis system that synthesizes structures from an abstract description written with VHDL behavioral constructs. The system uses components from a generic component library (GENUS), which can be mapped into a user defined technology library. The output of BdA is in structural VHDL and could be verified using a commercial VHDL simulator. The designer can control the synthesis process by providing different resource constraints to the system. BdA is also capable of producing different architectures which can be selected by the designer

Behavioral design assistant (BdA) user's manual : version 1.0

This report provides instructions for installing and using the Behavioral Design Assistant (BdA). BdA is a behavioral synthesis system that synthesizes structures from an abstract description written with VHDL behavioral constructs. The system uses components from a generic component library (GENUS), which can be mapped into a user defined technology library. The output of BdA is in structural VHDL and could be verified using a commercial VHDL simulator. The designer can control the synthesis process by providing different resource constraints to the system. BdA is also capable of producing different architectures which can be selected by the designer