Strength and durability properties of nanometakolined ultra high performance concrete (UHPC) using response surface model (RSM) approach

Utilisation of Ultra High Performance Concrete (UHPC) is growing an interest in the world of construction today. Apart from that the inclusion of nano material in UHPC can enhance the performance and durability of UHPC. In this study, effect of nano metakaolin as additive in UHPC is reported. Inclusion of nano metakaolin from 1, 3, 5, 7 and 9% from weight of cement is compared to those plain UHPC and metakaolined UHPC. Effect of nano metakaolin in UHPC is done by four consecutive testing namely compressive strength, flexural strength, porosity and water absorption. All samples are prepared for testing’s from 3, 7, 28, 90, 180 and 365 days and subjected to water cure until age of testing. For analysis, Response Surface Model using historical data software is selected. A new equation is generated to relate on the effect of nano metakaolin in UHPC

Ultra high-performance concrete as alternative repair method: A review

This review paper discussed on the behavior of Ultra High-Performance Concrete (UHPC) in the concrete industry. Since the emergence of unique design of concrete, the needs of UHPC can contribute to alternative solutions to the High-Performance Concrete (HPC) and also normal concrete. In this review, definition, materials and techniques of producing, chemical analysis, and prediction software on previous and current works of UHPC were presented. Moreover, in this paper, the benefits of UHPC as compared to the types of concrete were also discussed. As a conclusion, UHPC needs to be implemented more in the construction nowadays. Extra strong, durable, and slimmer design of concrete structures can be an alternative to a sustainable and economic design that can last longer with less supervision

Selective formation of tungsten nanowires

We report on a process for fabricating self-aligned tungsten (W) nanowires with polycrystalline silicon core. Tungsten nanowires as thin as 10 nm were formed by utilizing polysilicon sidewall transfer technology followed by selective deposition of tungsten by chemical vapor deposition (CVD) using WF6 as the precursor. With selective CVD, the process is self-limiting whereby the tungsten formation is confined to the polysilicon regions; hence, the nanowires are formed without the need for lithography or for additional processing. The fabricated tungsten nanowires were observed to be perfectly aligned, showing 100% selectivity to polysilicon and can be made to be electrically isolated from one another. The electrical conductivity of the nanowires was characterized to determine the effect of its physical dimensions. The conductivity for the tungsten nanowires were found to be 40% higher when compared to doped polysilicon nanowires of similar dimensions

Investigation On Inter-Layer Dielectric Processed By Chemical Mechanical Polishing And Spin-On Dielectric For Complementary Metal-Oxide-Semiconductor Compatible Devices

Surface planarization of the thin film layers that constitute the interconnects in the backend process of integrated circuit (IC) has become a critical need with the increasing number of metal levels. Planarization, globally and locally, needs to be achieved using the most efficient planarization methods available in the complementary metal oxide semiconductor (CMOS) IC fabrication industry. Spin-on dielectric (SOD) coating is a planarization method has long been used by the semiconductor industry. Since it uses liquid silica precursor, it creates particle defects either during storage or coating process because the evaporation of the liquid solvent leaves solid particles. The planarization degree is acceptable at sub-micron gap width but becomes worse at wider gap width. Chemical mechanical polishing (CMP) is another planarization method that is used by semiconductor industry for dielectric polishing. It is found that CMP is suitable to achieve desirable planarization with no particle defects as SOD, however it suffers microscratches, dishing, erosion and inefficient post-CMP cleaning. CMP planarization works by removing thin film using etching slurry and pressure applied on the wafer and it does not introduce any new dielectric material. This work is to investigate and improve the particle defects and the surface planarization of interlayer dielectric (ILD) using CMP, and also to investigate the electrical properties of the metal interconnect within the ILDs planarized by the SOD and CMP

High Voltage Graphene Nanowall Trench MOS Barrier Schottky Diode Characterization for High Temperature Applications

Graphene’s superior electronic and thermal properties have gained extensive attention from research and industrial sectors to study and develop the material for various applications such as in sensors and diodes. In this paper, the characteristics and performance of carbon-based nanostructure applied on a Trench Metal Oxide Semiconductor MOS barrier Schottky (TMBS) diode were investigated for high temperature application. The structure used for this study was silicon substrate with a trench and filled trench with gate oxide and polysilicon gate. A graphene nanowall (GNW) or carbon nanowall (CNW), as a barrier layer, was grown using the plasma enhanced chemical vapor deposition (PECVD) method. The TMBS device was then tested to determine the leakage current at 60 V under various temperature settings and compared against a conventional metal-based TMBS device using TiSi2 as a Schottky barrier layer. Current-voltage (I-V) measurement data were analyzed to obtain the Schottky barrier height, ideality factor, and series resistance (Rs) values. From I-V measurement, leakage current measured at 60 V and at 423 K of the GNW-TMBS and TiSi2-TMBS diodes were 0.0685 mA and above 10 mA, respectively, indicating that the GNW-TMBS diode has high operating temperature advantages. The Schottky barrier height, ideality factor, and series resistance based on dV/dln(J) vs. J for the GNW were calculated to be 0.703 eV, 1.64, and 35 ohm respectively