Alien Registration- Roherty, Marie (Portland, Cumberland County)

https://digitalmaine.com/alien_docs/24272/thumbnail.jp

Use of air gap structures to lower intralevel capacitance

Interconnect delays, arising in part from intralevel capacitance, are one of the factors limiting the performance of advanced circuits. In addition, the problem of filling the spaces between neighboring metal lines with an insulator is becoming increasingly acute as aspect ratios increase. We address these problems simultaneously by intentionally creating an air gap between closely spaced metal lines. Undesirable topography is eliminated using a spin-on dielectric. We then cap the wafers with silicon dioxide and planarize using chemical mechanical polishing. Simple modeling of test structures predicts an equivalent dielectric constant of 1.9 on features similar to those expected for 0.25 micron technologies. Two level metal test structures fabricated in a 0.5 micron CMOS technology show that the process can be readily integrated with current standard CMOS processes. The potential problems of via misalignment, overall dielectric stack height, and the relative difficulty of ensuring void formation compared to that of ensuring a void-free fill are considered

Lowering of intralevel capacitance using air gap structures

Interconnect delays, arising in part from intralevel capacitance, are one of the limiting factors in the performance of advanced integrated circuits. In addition, the problem of filling the spaces between neighboring metal lines with an insulator is becoming increasingly severe as aspect ratios increase. We address these problems by intentionally creating a air gap between closely spaced metal lines. The ends of the air gap and reentrant features are then sealed using a spin on dielectric. The entire structure is then capped with silicon dioxide and planarized . Simple modeling of mechanical test structures on silicon predicts an equivalent dielectric constant of 1.9 on features similar to those expected for 0.25 micron technologies. Metal to metal test structures fabricated in a 0.5 micron CMOS technology show that the process can be readily integrated with chemical mechanical polishing and current standard CMOS processes

Growth and properties of W-B-N diffusion barriers deposited by chemical vapor deposition

The authors have used chemical vapor deposition to grow ternary tungsten-based diffusion barriers to determine if they exhibit properties similar to those of sputter-deposited ternaries. A range of different W-B-N compositions in a band of compositions roughly between 20 and 40% W were produced. The deposition temperature was low, 350 C, and the precursors used are well accepted by the industry. Deposition rates are high for a diffusion barrier application. Resistivities range from 200 to 20,000 {micro}{Omega}-cm, the films with the best barrier properties having {approximately}1,000 {micro}{Omega}-cm resistivities. Adhesion to oxides is sufficient to allow these films to be used as the adhesion layer in a tungsten chemical mechanical polishing plug application. The films are x-ray amorphous as-deposited and have crystallization temperatures of up to 900 C. Barrier performance against Cu has been tested using diode test structures. A composition of W{sub .23}B{sub .49}N{sub .28} was able to prevent diode failure up to a 700 C, 30 minute anneal. These materials, deposited by CVD, display properties similar to those deposited by physical deposition techniques

Reversing the Balance Wheel Principle

The paper discusses funding principles and policies of higher education during the recession period. The role of state appropriations for the viability of public higher education institutions is emphasized. State funding affecting institutional behaviour is another issue raised. The paper analyzes the possibility of expanding state funding for higher education institutions instead of cutting during economic recession. The examples of Midwestern states is discussed for this purpose. Funding higher education institutions is perceived as an important component of the process of investing in human capital. Referring to scholarly findings, Leader-Laggard Model and Event History Analysis are suggested as optimal methods for evaluating the implementation of new policies as they spread from one state to another

Higher Education Funding Issues: U.S. / UK Comparison

The paper compares and contrasts higher education funding sources and systems in the U.S. and the UK. The issues raised in the paper pertain to the major challenge of academia: finding financial support in times of limited resources and enhanced competition. The issues discussed throughout the paper are: funding and quality assessment of universities; funding and equity of access to post-secondary education; marketization and privatization of universities; funding, autonomy and accountability of higher education institutions

Alien Registration- Roherty, Marie (Portland, Cumberland County)

https://digitalmaine.com/alien_docs/24272/thumbnail.jp

Alien Registration- Roherty, Austin J. (Portland, Cumberland County)

https://digitalmaine.com/alien_docs/21646/thumbnail.jp