Characterization of fast relaxation by oxide-trapped charges under BTI stress on 64 nm HfSiON/SiO2 MOSFETs

For HfSiON/SiO2 n-type and p-type MOSFETs with a channel length L = 64 nm, the fast relaxation effect of oxide-trapped charges Q(ox) during interrupt for bias temperature instability (BTI) degradation measurement were investigated, and a model that compensated for this effect to predict lifetime t(L) was proposed. Experimental results show that the fast relaxation of Qox during threshold-voltage V-th measurement rapidly saturates within 1 s and is exponentially increasing for gate stress voltage V-g,V-str and exponentially decreasing for measurement duration t(m) but does not affect the BTI degradation mechanism. Using the V-g,V-str and t(m) dependence of Q(ox's) fast relaxation under BTI stress, t(L) prediction model was proposed to compensate the recovery effect by V-th measurement from BTI degradation measured in slow measurement (SM) condition with t(m) > 1 mu s. The proposed model increases the precision of the estimate of t(L) by considering the recovery effect of Qox even in SM. (C) 2020 The Japan Society of Applied Physics11Nsciescopu

Systematic analysis of electron traps of HfSiON/SiO2 nMOSFETs using TSCIS

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Channel-length dependence of the generation of interface states and oxide-trapped charges on drain avalanche hot carrier degradation of HfSiON/SiO2 p-channel MOSFETs with strained Si/SiGe channel

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Characterization of positive bias temperature instability concerning interfacial layer thickness of HfSiON/SiO2 nMOSFET

This paper investigates how interfacial layer (IL) thickness of HfSiON/SiO2 nMOSFETs affects their responses to positive bias temperature instability. Experimental results show that stress-induced traps and secondary-hole trapping were generated more in a thicker IL nMOS than in a thinner IL nMOS. From these results, the thicker IL nMOS had larger threshold voltage-shift AVd, and lower time exponent n than the thinner IL nMOS at the same oxide field E. At high E, the thicker IL nMOS had shorter lifetime (t(L)) due to larger Delta V-th than the thinner IL nMOS. At low E-ox, related to operating voltage, the thicker IL nMOS had longer tL due to lower n than the thinner IL nMOS. Thus, thickening the IL is applicable to increase t(L) of HfSiON/SiO2 nMOSFET.11Nsciescopu

Channel-length dependence of mechanical stress effect by hybrid shallow trench isolation on NBTI degradation of HfSiON/SiO2 p-channel MOSFETs with strained Si/SiGe channel

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Effect of HfSiON thickness on electron trap distributions of HfSiON/SiO2 nMOSFET under PBTI

The effect of HfSiON thickness on electron trap distributions under positive bias temperature instability (PBTI) was investigated in HfSiON/SiO2 nMOSFET. Trap distributions of HfSiON/SiO2 nMOSFET were observed by charging and discharging electrons at pre-existing or newly-generated traps. Experimental results show that the peak values of electron trap density shifted to deeper electron trap energy level (E-t) with increasing stress field E-str and stress time t(s). Compared to the Thick HfSiON device, the Thin HfSiON device had lower trap density and slower Et-shift; as a result, the Thin HfSiON device had lower threshold voltage-shift Delta Vth and larger power-law time exponent n of PBTI than the Thick HfSiON device. Low Delta Vth is beneficial for lifetime of HfSiON/SiO2 nMOSFET but large n is not, so the effect of HfSiON thickness on distribution of electron trap must be quantified to enable optimization of HfSiON thickness to yield reliable HfSiON/SiO2 nMOSFETs.11Nsciescopu

Characterization of Positive Bias Temperature Instability Concerning Interfacial Layer Thickness of HfSiON/SiO2 nMOSFET

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Fast and accurate method of lifetime estimation for HfSiON/SiO2 dielectric n-MOSFETs under positive bias temperature instability

This paper proposes a fast and accurate method to measure the constants a and n of the power law Delta V-th = at(n) for HfSiON/SiO2 dielectric nMOSFETs under positive bias temperature instability (PBTI), where Delta V-th is a shift of threshold voltage, and t is stress duration. The proposed method requires one nMOSFET only, uses a voltage ramp stress (VRS),measures Delta V-th vs. t data during VRS, uses a regression method to fit the data for each VRS pulse to the power law to obtain a and n at each stress voltage V-g,V-str,,then obtains five voltage-independent constants for the power law after fitting the curves of a and n vs. V-g,V-str to empirical models. The five voltage-independent constants agreed very well with those obtained using the constant voltage stress (CVS) method. After obtaining the voltage-independent constants, the lifetime t(L) at an operating voltage V-op was estimated using the power law. The estimated t(L) = 1.67 x 10(8) s was quite close to t(L) = 1.74 x 10(8) s estimated using CVS, and to t(L) = 1.72 x 10(8) s estimated by extrapolating the Delta V-th vs. t curve measured at V-g,V-str = V-op = 1.2 V to Delta V-th = 200 mV. The time required for measurement was 900 s, compared to 30,000 s for the CVS method. These experimental results show that the proposed VRS-regression method is very useful for screening nMOSFETs under PBTI.11Nsciescopu