Partial regularity for a surface growth model

We prove two partial regularity results for the scalar equation $u_t+u_{xxxx}+\partial_{xx}u_x^2=0$, a model of surface growth arising from the physical process of molecular epitaxy. We show that the set of space-time singularities has (upper) box-counting dimension no larger than $7/6$ and $1$-dimensional (parabolic) Hausdorff measure zero. These parallel the results available for the three-dimensional Navier--Stokes equations. In fact the mathematical theory of the surface growth model is known to share a number of striking similarities with the Navier--Stokes equations, and the partial regularity results are the next step towards understanding this remarkable similarity. As far as we know the surface growth model is the only lower-dimensional "mini-model" of the Navier--Stokes equations for which such an analogue of the partial regularity theory has been proved. In the course of our proof, which is inspired by the rescaling analysis of Lin (1998) and Ladyzhenskaya & Seregin (1999), we develop certain nonlinear parabolic Poincar\'e inequality, which is a concept of independent interest. We believe that similar inequalities could be applicable in other parabolic equations.Comment: 29 page

Robustness of Regularity for the 33D Convective Brinkman-Forchheimer Equations

We prove a robustness of regularity result for the $3$D convective Brinkman-Forchheimer equations \partial_tu -\mu\Delta u + (u \cdot \nabla)u + \nabla p + \alpha u + \beta\abs{u}^{r - 1}u = f, for the range of the absorption exponent $r \in [1, 3]$ (for $r > 3$ there exist global-in-time regular solutions), i.e. we show that strong solutions of these equations remain strong under small enough changes of the initial condition and forcing function. We provide a smallness condition which is similar to the robustness conditions given for the $3$D incompressible Navier-Stokes equations by Chernyshenko et al. (2007) and Dashti & Robinson (2008).Comment: 22 page

The SPAR thermal analyzer: Present and future

The SPAR thermal analyzer, a system of finite-element processors for performing steady-state and transient thermal analyses, is described. The processors communicate with each other through the SPAR random access data base. As each processor is executed, all pertinent source data is extracted from the data base and results are stored in the data base. Steady state temperature distributions are determined by a direct solution method for linear problems and a modified Newton-Raphson method for nonlinear problems. An explicit and several implicit methods are available for the solution of transient heat transfer problems. Finite element plotting capability is available for model checkout and verification

Diode laser 87Rb optical pumping in an evacuated wall-coated cell

The evacuated wall coated sealed cell coupled with diode laser optical pumping offers a number of attractive potential advantages for use in Rb or Cs atomic frequency standards. An investigation of systematic effects is required to explore possible limitations of the technique. The use of diode laser optical pumping of 87 Rb in an evacuated wall coated sealed cell is presented. Experimental results/discussion to be presented include the signal strength and line broadening of the 0 - 0 hyperfine resonance as a function of light intensity for the D1 optical transitions (F - F prime) - (2 1 prime) and (2 - 2 prime), shift of the 0 - 0 hyperfine frequency as a function of laser intensity and de-tuning from optical resonance, and diode laser frequency stabilization techniques

A 128K-bit CCD buffer memory system

A prototype system was implemented to demonstrate that CCD's can be applied advantageously to the problem of low power digital storage and particularly to the problem of interfacing widely varying data rates. 8K-bit CCD shift register memories were used to construct a feasibility model 128K-bit buffer memory system. Peak power dissipation during a data transfer is less than 7 W., while idle power is approximately 5.4 W. The system features automatic data input synchronization with the recirculating CCD memory block start address. Descriptions are provided of both the buffer memory system and a custom tester that was used to exercise the memory. The testing procedures and testing results are discussed. Suggestions are provided for further development with regards to the utilization of advanced versions of CCD memory devices to both simplified and expanded memory system applications