Parallel Multithread Analysis of Extremely Large Simulation Traces

With the explosion in the size of off-the-shelf integrated circuits and the advent of novel techniques related to failure modes, commercial Automatic Test Pattern Generator and fault simulation engines are often insufficient to measure the coverage of particular metrics. Consequently, a general working framework consists of storing simulation traces during the analysis phase and collecting test statistics from post-processing. Unfortunately, typical simulation traces can be hundreds of gigabytes long, and their analysis can require several days, even on large and powerful computational servers. In this paper, we propose a set of strategies to mitigate the evaluation time and the memory needed to analyze huge dump files stored in the standard Value Change Dump format. We concentrate on burn-in-related metrics that current commercial fault simulators and Automatic Test Pattern Generators cannot evaluate. We show how to divide the analysis process into several concurrent pipeline stages. We revise the logic process of each stage and all principal intermediate data structures, to adopt smart parallelization with very low contention and extremely low overhead. We exploit several low-level optimizations from modern programming techniques to reduce computation time and balance the different pipeline phases. We analyze simulation traces up to almost 250 GBytes computing different testing metrics. Overall, we can keep under control the memory usage, and we show time improvements of over two orders of magnitude compared to previously adopted state-of-the-art tools

Test, Reliability and Functional Safety Trends for Automotive System-on-Chip

This paper encompasses three contributions by industry professionals and university researchers. The contributions describe different trends in automotive products, including both manufacturing test and run-time reliability strategies. The subjects considered in this session deal with critical factors, from optimizing the final test before shipment to market to in-field reliability during operative life

S7 - An Optimized Burn-In Stress Flow targeting Interconnections logic to Embedded Memories in Automotive Systems-on-Chip

The complexity of automotive Systems-on-a-Chip (SoCs) has enormously grown in the last decades. Today’s automotive SoCs are compelling due to technology improvements, different integration technologies, increased heterogeneity, and many available embedded memories. On balance, despite testing techniques that have been refined through years, traditional structural test methods, like scan and BIST, can cover a vast but not complete spectrum of all the possible defects. It appears that the divide-and-conquer approach founded on structural techniques may not be enough to reach every single element or to effectively stimulate the faulty behaviors that may show up during the lifetime of the device. Burn-In is widely used to reduce Infant Mortality, accelerating the evolution of weak points into defects via externally or internally induced stress. In this work, we focus on internal stress and present a generation strategy intended to automatically produce functional stress procedures for the Burn-In phase that exacerbate possible weak points which are likely to escape activation by structural tests, such that they more easily outbreak during the successive final test procedures. The proposed generation strategy primarily addresses the interconnections to embedded memories, which look challenging to stress by structural methods, including Logic and Memory BIST, and critical due to the integration of different technologies (i.e., logic gates and memory layout). In the considered test case, the proposed approach increases the average toggle activity by orders of magnitude with respect to Memory BIST. Furthermore, it provides a uniform distributed toggling activity. Results collected on an automotive SoC show how the stress provided by functional programs compares with the stress level provided by structural test methods measured in terms of toggling activity. The SpeedUp produced by the proposed procedure is 3.14X wrt to the MBIST executing the March C-algorithm

Accelerated Analysis of Simulation Dumps through Parallelization on Multicore Architectures

With the explosion of off-the-shelf SoCs in terms of size and the advent of novel techniques related to failure modes, commercial ATPG and fault simulation engines can often be insufficient to measure the coverage of very specific metrics. In these cases, many researchers firstly store the simulation trace during the analysis phase. Then, they collect the desired statistics during a post-processing step. In this framework, the so-called Value Change Dump (VCD) is a very commonly used file format to record simulation traces. The target of this paper is twofold. From the one hand, we illustrate some Burn-In (BI) related metrics which cannot be evaluated by current commercial fault simulators and ATPG engines. These metrics are indeed based on a post-processing analysis of memory dumps in VCD format. From the other hand, we mitigate the evaluation time and the memory required to analyze huge VCD files by exploiting optimization techniques coming from modern programming features and smart parallelization. Adopting this strategy, we can analyze simulation dumps of more than 250 GBytes in less than one hour, showing improvements of two orders of magnitude over previous tools, with a consequent higher scalability and testability power

A novel SEU injection setup for Automotive SoC

The world of embedded electronic systems is increasingly part of everyone's daily life. Therefore, the production of chip and embedded systems is becoming more complex and massive in recent years. This aspect is also responsible for the continuous and rapid growth of abnormal system behaviors. This paper aims to propose an automated setup that connects Functional Testing and Scan Technique, exploiting the versatility of the functional environment and the Design-for-Testability to reduce the time needed for the evaluation of device SEUs effects. Preliminary experimental results show it is possible to inject a single SEU in milliseconds while keeping high accuracy

Test, Reliability and Functional Safety trends for Automotive System-on-Chip

This paper encompasses three contributions by industry professionals and university researchers. The contributions describe different trends in automotive products, including both manufacturing test and run-time reliability strategies. The subjects considered in this session deal with critical factors, from optimizing the final test before shipment to market to in-field reliability during operative life

SP2 - Test, Reliability and Functional Safety Trends for Automotive System-on-Chip

This paper encompasses three contributions by industry professionals and university researchers. The contributions describe different trends in automotive products, including both manufacturing test and run-time reliability strategies. The subjects considered in this session deal with critical factors, from optimizing the final test before shipment to market to in-field reliability during operative life