Grain Boundaries in Graphene on SiC(0001ˉ\bar{1}) Substrate

Grain boundaries in epitaxial graphene on the SiC(000$\bar{1}$) substrate are studied using scanning tunneling microscopy and spectroscopy. All investigated small-angle grain boundaries show pronounced out-of-plane buckling induced by the strain fields of constituent dislocations. The ensemble of observations allows to determine the critical misorientation angle of buckling transition $\theta_c = 19 \pm~2^\circ$. Periodic structures are found among the flat large-angle grain boundaries. In particular, the observed $\theta = 33\pm2^\circ$ highly ordered grain boundary is assigned to the previously proposed lowest formation energy structural motif composed of a continuous chain of edge-sharing alternating pentagons and heptagons. This periodic grain boundary defect is predicted to exhibit strong valley filtering of charge carriers thus promising the practical realization of all-electric valleytronic devices

Selective growth of CdTe on patterned CdTe/Si(211)

The authors have studied selective growth of cadmium telluride on Si(211) by molecular beam epitaxy (MBE). Patterned substrates were produced by optical lithography of MBE-grown CdTe/As/Si(211). Photoemission microscopy was used as the main tool to study selective growth. This is very powerful because Si or SiO2 can be very easily distinguished from areas covered with even small amounts of CdTe due to contrast from work function differences. It was found that CdTe grows on CdTe without sticking on bare Si areas if the temperature is sufficiently high. Based on the analysis of the temperature dependence of the growth rate of CdTe, we suggest that different physisorption energies on Si and CdTe are the main cause of this selective growth. (C) 2008 American Vacuum Society

Strain reduction in selectively grown CdTe by MBE on nanopatterned silicon on insulator (SOI) substrates

Silicon-based substrates for the epitaxy of HgCdTe are an attractive low-cost choice for monolithic integration of infrared detectors with mature Si technology and high yield. However, progress in heteroepitaxy of CdTe/Si (for subsequent growth of HgCdTe) is limited by the high lattice and thermal mismatch, which creates strain at the heterointerface that results in a high density of dislocations. Previously we have reported on theoretical modeling of strain partitioning between CdTe and Si on nanopatterned silicon on insulator (SOI) substrates. In this paper, we present an experimental study of CdTe epitaxy on nanopatterned (SOI). SOI (100) substrates were patterned with interferometric lithography and reactive ion etching to form a two-dimensional array of silicon pillars with similar to 250 nm diameter and 1 mu m pitch. MBE was used to grow CdTe selectively on the silicon nanopillars. Selective growth of CdTe was confirmed by scanning electron microscopy (SEM), atomic force microscopy (AFM), and X-ray photoelectron spectroscopy (XPS). Coalescence of CdTe on the silicon nanoislands has been observed from the SEM characterization. Selective growth was achieved with a two-step growth process involving desorption of the nucleation layer followed by regrowth of CdTe at a rate of 0.2 angstrom s(-1). Strain measurements by Raman spectroscopy show a comparable Raman shift (2.7 +/- 2 cm(-1) from the bulk value of 170 cm(-1)) in CdTe grown on nanopatterned SOI and planar silicon (Raman shift of 4.4 +/- 2 cm(-1)), indicating similar strain on the nanopatterned substrates