An Evolved Wavelet Library Based on Genetic Algorithm

As the size of the images being captured increases, there is a need for a robust algorithm for image compression which satiates the bandwidth limitation of the transmitted channels and preserves the image resolution without considerable loss in the image quality. Many conventional image compression algorithms use wavelet transform which can significantly reduce the number of bits needed to represent a pixel and the process of quantization and thresholding further increases the compression. In this paper the authors evolve two sets of wavelet filter coefficients using genetic algorithm (GA), one for the whole image portion except the edge areas and the other for the portions near the edges in the image (i.e., global and local filters). Images are initially separated into several groups based on their frequency content, edges, and textures and the wavelet filter coefficients are evolved separately for each group. As there is a possibility of the GA settling in local maximum, we introduce a new shuffling operator to prevent the GA from this effect. The GA used to evolve filter coefficients primarily focuses on maximizing the peak signal to noise ratio (PSNR). The evolved filter coefficients by the proposed method outperform the existing methods by a 0.31 dB improvement in the average PSNR and a 0.39 dB improvement in the maximum PSNR

A NOVEL ARCHITECTURE FOR VLIW PROCESSOR

Technology has seen the development of processor industry right from micro to the latest Nanotechnology with speed being important criteria. Not much attention has been given to the power required to drive these Integrated Circuits. With gaining popularity in mobile computing, developing mobile processors have gained popularity since these processors possess unique properties like low power consumption and dissipation. This paper aims at designing a low power Very Long Instruction Word (VLIW) processor with built in FFT processor, which uses single clock frequency. This VLIW processor is designed with two modules one for VLIW processor and the other one is Hybrid dynamic voltage scaling module. Using the DVS algorithm the power can be reduced up to 20 to 25 % of normal VLIW processor. The design is simulated and synthesized using Xilinx project Navigator and the report is given in the paper

High performance ACS for Viterbi decoder using pipeline T-Algorithm

Viterbi algorithm is the most popular algorithm used to decode the convolution code, but its computational complexity increases exponentially with the increasing constraint length due to the large number of Trellis transitions. However, high constraint length is necessary to improve the accuracy of the decoding process for the high rate convolution code. In particular, the Add Compare Select (ACS) module of the Viterbi Decoder will have large numbers of trellis states and trellis transitions with increased constraint lengths, which give rise to high hardware complexity and large power consumption. As the performance of Viterbi decoder mainly depends on its efficient implementation of ACS module, in this paper, we propose a modified pipelined architecture for the ACS of Viterbi decoder. This is derived by employing the technique of re-timing; further the architecture is also reconfigured to support various wireless standards. The architecture has been implemented in Xilinx Vertex 6 FPGA device to make the comparison between our architecture and the existing architecture. From the analysis done on ACS implementation, it is found that the resource requirements, delay and power consumption are optimized significantly for the proposed architecture compared to existing pipelined architecture. The results obtained from the analysis show that frequency of the system is increased up to 165 MHz with reduced area. The cell level performance is also obtained using Cadence Encounter (R) tool with TSMC 180 nm CMOS technology