Translating expert system rules into Ada code with validation and verification

The purpose of this ongoing research and development program is to develop software tools which enable the rapid development, upgrading, and maintenance of embedded real-time artificial intelligence systems. The goals of this phase of the research were to investigate the feasibility of developing software tools which automatically translate expert system rules into Ada code and develop methods for performing validation and verification testing of the resultant expert system. A prototype system was demonstrated which automatically translated rules from an Air Force expert system was demonstrated which detected errors in the execution of the resultant system. The method and prototype tools for converting AI representations into Ada code by converting the rules into Ada code modules and then linking them with an Activation Framework based run-time environment to form an executable load module are discussed. This method is based upon the use of Evidence Flow Graphs which are a data flow representation for intelligent systems. The development of prototype test generation and evaluation software which was used to test the resultant code is discussed. This testing was performed automatically using Monte-Carlo techniques based upon a constraint based description of the required performance for the system

Enhancing hole mobility in III-V semiconductors

Transistors based on III-V semiconductor materials have been used for a variety of analog and high frequency applications driven by the high electron mobilities in III-V materials. On the other hand, the hole mobility in III-V materials has always lagged compared to group-IV semiconductors such as silicon and germanium. In this paper we explore the used of strain and heterostructure design guided by bandstructure modeling to enhance the hole mobility in III-V materials. Parameters such as strain, valence band offset, effective masses and splitting between the light and heavy hole bands that are important for optimizing hole transport are measured quantitatively using various experimental techniques. A peak Hall mobility for the holes of 960cm2/Vs is demonstrated and the high hole mobility is maintained even at high sheet charge.Comment: 18 pages, 21 figure

Understanding endurance degradation in Flash memory through transconductance measurement

Endurance degradation is a limitation for implementing futurescaled flash memory devices. This degradation is mainly attributableto Si/SiO2 interface traps generated during program/erase (P/E) stress rather than fixed charges in the bulk oxide. In this work, we use Gm (transconductance) to monitor the interface degradation. Wereport that interface defect generation is highest during erase operation. In addition to the interface, hole & electron tunnelingprobability seem crucial to degradation during erase. Fluorine incorporation in tunnel stack is found to reduce Gm degradationsuggesting improved interface

A Novel Fluorine Incorporated Band Engineered (BE) Tunnel (SiO2/ HfSiO/ SiO2) TANOS with Excellent Program/Erase & Endurance to 10^5 Cycles

We demonstrate for the first time a fluorine incorporated band- engineered (BE) tunnel oxide (SiO2/HfSiO/SiO2) TANOS with excellent program / erase (P/E) characteristics and endurance to 105 cycles. Incorporating fluorine in the tunnel dielectric improves Si/SiO2 interface resulting in excellent endurance of nearly constant over 3 V P/E window for at least 105 cycles. Fluorine also reduces interface state generation during retention by ~20%. Furthermore, Fluorine passivates bulk traps leading to as much as ~10times higher charge to breakdown (Qbd) and ~10-50times lower interface state density (Dit). Fluorine passivation for BE-TANOS is significant because it improves reliability assisting implementation of TANOS flash NVM beyond the 20 nm node