Scaling analysis of electron transport through metal-semiconducting carbon nanotube interfaces: Evolution from the molecular limit to the bulk limit

We present a scaling analysis of electronic and transport properties of metal-semiconducting carbon nanotube interfaces as a function of the nanotube length within the coherent transport regime, which takes fully into account atomic-scale electronic structure and three-dimensional electrostatics of the metal-nanotube interface using a real-space Green's function based self-consistent tight-binding theory. As the first example, we examine devices formed by attaching finite-size single-wall carbon nanotubes (SWNT) to both high- and low- work function metallic electrodes through the dangling bonds at the end. We analyze the nature of Schottky barrier formation at the metal-nanotube interface by examining the electrostatics, the band lineup and the conductance of the metal-SWNT molecule-metal junction as a function of the SWNT molecule length and metal-SWNT coupling strength. We show that the confined cylindrical geometry and the atomistic nature of electronic processes across the metal-SWNT interface leads to a different physical picture of band alignment from that of the planar metal-semiconductor interface. We analyze the temperature and length dependence of the conductance of the SWNT junctions, which shows a transition from tunneling- to thermal activation-dominated transport with increasing nanotube length. The temperature dependence of the conductance is much weaker than that of the planar metal-semiconductor interface due to the finite number of conduction channels within the SWNT junctions. We find that the current-voltage characteristics of the metal-SWNT molecule-metal junctions are sensitive to models of the potential response to the applied source/drain bias voltages.Comment: Minor revision to appear in Phys. Rev. B. Color figures available in the online PRB version or upon request to: [email protected]

Studying complex interventions : reflections from the FEMHealth project on evaluating fee exemption policies in West Africa and Morocco

Peer reviewedPublisher PD

Event-Based Thermal Control for High Power Density Microprocessors

This chapter presents the proposed event-based thermal control solution at the HARPA-RT level, thus complementing the previous chapter which dealt with the same topic at the HARPA-OS level. A brief analysis of the thermal control problem is presented, evidencing as the main requirement the need for thermal control at the millisecond timescale, caused by software variability in the use of CPU functional resources and fast thermal dynamics inside the silicon die. To meet this requirement while keeping a low overhead, the proposed solution consists of a hardware state machine and datapath that monitors temperature and generates interrupts, and a software policy built using event-based control theory. This partition provides both a fast response to critical and unpredictable temperature increases, a very low overhead when temperature is low or almost constant, and the flexibility of a software implementation of the control policy. The proposed solution is evaluated both in simulation using the Modelica modelling language, and on a commercial Intel CPU

Insulated-gate Field-effect Transistors

served as the basis for further development leading to FET memory. Designs and characteristics of experimental devices of 500 and 1000 A gate insulator thicknesses are presented, with particular attention to the effects of source-drain spacing