18 research outputs found
Molecular velocity auto-correlation of simple liquids observed by NMR MGSE method
The velocity auto-correlation spectra of simple liquids obtained by the NMR
method of modulated gradient spin echo show features in the low frequency range
up to a few kHz, which can be explained reasonably well by a long
time tail decay only for non-polar liquid toluene, while the spectra of polar
liquids, such as ethanol, water and glycerol, are more congruent with the model
of diffusion of particles temporarily trapped in potential wells created by
their neighbors. As the method provides the spectrum averaged over ensemble of
particle trajectories, the initial non-exponential decay of spin echoes is
attributed to a spatial heterogeneity of molecular motion in a bulk of liquid,
reflected in distribution of the echo decays for short trajectories. While at
longer time intervals, and thus with longer trajectories, heterogeneity is
averaged out, giving rise to a spectrum which is explained as a combination of
molecular self-diffusion and eddy diffusion within the vortexes of hydrodynamic
fluctuations.Comment: 8 pages, 6 figur
A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI
An 800-MHz Mixed-V-T 4T IFGC Embedded DRAM in 28-nm CMOS Bulk Process for Approximate Storage Applications
773 SINGLE-CHAIN ANTIBODIES INHIBIT HCV INFECTIOUS VIRUS REPLICATION BY PROTEIN DELIVERY
64-kB 65-nm GC-eDRAM With Half-Select Support and Parallel Refresh Technique
Gain-cell-embedded DRAM (GC-eDRAM) is an attractive alternative to traditional 6T SRAM, as it offers higher density, lower leakage power, and two-ported functionality. However, its refresh requirement also results in power consumption and memory access limitations. In this letter, we present a GC-eDRAM architecture designed to overcome the refresh disadvantages using a novel technique for improving the availability of the memory. In addition, by using a read-before-write mechanism, half select is supported. The macro avoids the need for supply boosting by employing 3T-1C bitcells and also integrates a replica bit line for optimal access timing to improve performance and power consumption. A 64- kB GC-eDRAM macro was fabricated in a 65- nm process technology, providing a 40% area reduction compared to a 6T SRAM cell, while achieving a 99.99% bit yield with a 16 mu s retention time
